ISL6596 Intersil Corporation, ISL6596 Datasheet
ISL6596
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ISL6596 Summary of contents
Page 1
... PHASE node rising edge, preventing power loss caused by the self turn-on of the lower MOSFET due to the high dV/dt of the switching node. The ISL6596 also features an input that recognizes a high- impedance state, working together with Intersil multi-phase 3. PWM controllers to prevent negative transients on the controlled output voltage when operation is suspended ...
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... Pinout ISL6596 (SOIC) TOP VIEW UGATE 1 BOOT 2 PWM 3 GND 4 Block Diagram VCC VCTRL PWM VCTRL = CONTROLLER VCC 2 ISL6596 8 PHASE 7 VCTRL 6 VCC 5 LGATE ISL6596 SHOOT- THROUGH 7k PROTECTION CONTROL LOGIC 7k ISL6596 (DFN) TOP VIEW 1 10 UGATE PHASE 2 9 BOOT VCTRL 3 8 N/C N PWM ...
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... Typical Application - Multi-Phase Converter Using ISL6596 Gate Drivers +3.3V +3.3V FB COMP VCC VSEN PWM1 PWM2 PGOOD PWM CONTROLLER (ISL69XX) ISEN1 VID (OPTIONAL) ISEN2 FS/EN GND R IS REQUIRED FOR SPECIAL POWER SEQUENCING APPLICATIONS UGPH 3 ISL6596 +5V BOOT VCC VCTRL UGATE PWM ISL6596 PHASE LGATE +5V BOOT VCC ...
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... Upper Drive Sink Resistance Lower Drive Source Resistance Lower Drive Sink Resistance NOTE: 4. Guaranteed by Characterization. Not 100% tested in production. 4 ISL6596 Thermal Information Thermal Resistance (Notes 1, 2, & 3) SOIC Package (Note DFN Package (Notes 2 & 3 -0. (DC) Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65° ...
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... RU UGATE LGATE 1V t PDLL 5 ISL6596 LGATE (Pin 5) Lower gate drive output. Connect to gate of the low side N-Channel power MOSFET. A gate resistor is never recommended on this pin interferes with the operation shoot-through protection circuitry. VCC (Pin 6) Connect this pin to a +5V bias supply. Locally bypass with a high quality ceramic capacitor to ground ...
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... MOSFET due to high dV/dt of the switching node. PWM Input and Threshold Control A unique feature of the ISL6596 is the programmable PWM logic threshold set by the control pin (VCTRL) voltage. The VCTRL pin should connect to the VCC of the controller, thus the PWM logic threshold follows with the voltage level of the controller ...
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... Q CC the driver without capacitive load and is typically negligible. 7 ISL6596 The total gate drive power losses are dissipated among the resistive components along the transition path. The drive resistance dissipates a portion of the total gate drive power losses, the rest will be dissipated by the external gate ...
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... ISL6596 Upper MOSFET Self Turn-On Effects At Startup Should the driver have insufficient bias voltage applied, its outputs are floating. If the input bus is energized at a high ...
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... D2 (DATUM B) D2 INDEX AREA (DATUM N (Nd-1)Xe REF. BOTTOM VIEW 0.415 NX (b) (A1) 5 SECTION "C-C" 9 ISL6596 2X L10.3x3 0. LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE 2X 0. SYMBOL 0. 0. NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 ISL6596 M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE ...