ISL8104 Intersil Corporation, ISL8104 Datasheet - Page 10

• Manufacturer Part Number: ISL8104
• Description: Synchronous Buck Pulse-Width Modulator (PWM) Controller
• Manufacturer: Intersil Corporation

It is recommended that a mathematical model be used to
plot the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G
compensation (G
COMPENSATION BREAK FREQUENCY EQUATIONS
Figure 8 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
G
F
F
2. Calculate C
3. Calculate C
4. Calculate R
Z1
Z2
MOD
G
G
FB
CL
at 0.1 to 0.75 of F
to the desired number). The higher the quality factor of the
output filter and/or the higher the ratio F
the F
C
C
such that F
times F
the regulator. Change the numerical factor (0.7) below to
reflect desired placement of this pole. Placement of F
lower in frequency helps reduce the gain of the
compensation network at high frequency, in turn reducing
the HF ripple component at the COMP pin and minimizing
resultant duty cycle jitter.
R
C
=
=
1
2
3
3
f ( )
f ( )
f ( )
------------------------------ -
2π R
-------------------------------------------------
2π
=
=
=
=
Z1
=
=
---------------------------------------------- -
2π R
------------------------------------------------------- -
2π R
--------------------- -
------------------------------------------------ -
2π R
=
F
----------- - 1
⋅
⋅
F
(
SW
SW
LC
1
R
frequency (to maximize phase boost at F
D
------------------------------ -
--------------------------------------------------- - ⋅
s f ( ) R
------------------------------------------------------------------------------------------------------------------------ -
(
G
R
2
1
⋅
⋅
⋅
1
1
MAX
MOD
1
⋅
+
V
). F
–
+
1
+
C
1
2
2
2
P2
3
3
OSC
⋅
s f ( ) R
1
R
such that F
s f ( ) R
⋅
⋅
⋅
such that F
1
such that F
FB
1
0.5 F
C
0.7 F
⋅
f ( ) G
3
C
SW
1
is placed below F
V
) C
1
1
⋅
⋅
) and closed-loop response (G
⋅
IN
⋅
LC
(
⋅
⋅
⋅
⋅
C
F
1
represents the switching frequency of
3
3
⋅
CE
2
1
LC
SW
+
FB
(to adjust, change the 0.5 factor below
⋅
---------------------------------------------------------------------------------------------------------- -
1
⋅
+
C
s f ( )
C
+
f ( )
–
C
3
Z1
1
s f ( )
)
P1
1
2
Z2
F
F
⋅
)
⋅
10
P1
P2



is placed at a fraction of the F
(
1
is placed at F
R
is placed at F
⋅
(
1
+
=
=
ESR
+
where s f ( )
s f ( ) R
1
-------------------------------------------- -
2π R
------------------------------ -
2π R
R
SW
+
3
s f ( ) ESR C
⋅
⋅
⋅
+
) C
⋅
DCR
1
,
(typically, 0.3 to 1.0
MOD
2
2
3
⋅
⋅
3
⋅
⋅
CE
1



-------------------- -
C
C
C
CE
-------------------- -
C
LC
C
) C
3
1
/F
1
), feedback
=
1
⋅
1
+
.
⋅
. Calculate C
LC
+
⋅
C
2π f j
⋅
C
C
C
+
2
, the lower
2
2
2
s
⋅ ⋅
CL



LC
2



f ( ) L C
):
).
⋅
LC
P2
⋅
3
ISL8104
,
compensation gain at F
amplifier. The closed loop gain, G
log-log graph of Figure 8 by adding the modulator gain,
G
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin. The mathematical model
presented makes a number of approximations and is
generally not accurate at frequencies approaching or
exceeding half the switching frequency. When designing
compensation networks, select target crossover frequencies
in the range of 10% to 30% of the switching frequency,
F
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
FIGURE 8. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
SW
MOD
0
.
LOG
(in dB), to the feedback compensation gain, G
20
log


R2
------- -
R1


F
Z1
F
F
P2
LC
Z2
against the capabilities of the error
F
F
CE
P1
CL
F
0
, is constructed on the
F
20
P2
log
G
CL
COMPENSATION GAIN
D
--------------------------------- -
OPEN LOOP E/A GAIN
CLOSED LOOP GAIN
MAX
G
V OSC
MODULATOR GAIN
MOD
FREQUENCY
⋅
February 13, 2006
V
IN
G
FB
FB
FN9257.0
(in