ISL95811 Intersil Corporation, ISL95811 Datasheet - Page 5

• Manufacturer Part Number: ISL95811
• Description: Single Digitally Controlled Potentiometer
• Manufacturer: Intersil Corporation

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Operating Specifications
NOTES:
4. Typical values are for T
5. LSB: [V(RW)
6. ZS error = V(RW)
7. FS error = [V(RW)
8. DNL = [V(RW)
Rpu (Note 16)
t
Cb (Note 16)
WC
incremental voltage when changing from one tap to an adjacent tap.
t
t
t
R
F
HD:STO:NV
SYMBOL
t
t
t
t
t
t
t
t
HD:DAT
SU:STO
HD:STO
(Note 16)
SU:STA
HD:STA
SU:DAT
(Note 16)
HD:WP
SU:WP
t
t
(Note 17)
f
t
HIGH
LOW
BUF
t
SCL
t
t
AA
DH
IN
255
i
– V(RW)
– V(RW)
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP Condition Hold Time for Read,
or Volatile Only Write
STOP Condition Hold Time for Non-
Volatile Write
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive Loading of SDA or SCL
SDA and SCL Bus Pull-Up Resistor
Off-Chip
Non-Volatile Write Cycle Time
WP Setup Time
WP Hold Time
0
255
/
LSB.
– V
A
i-1
= +25°C and 3.3V supply voltage.
0
CC
]
]
/
/
LSB-1, for i = 1 to 255. i is the DCP register setting.
255. V(RW)
]
PARAMETER
/
5
LSB.
Over the recommended operating conditions unless otherwise specified. (Continued)
255
and V(RW)
0
Measured at the 30% of V
SCL rising edge to SDA falling edge. Both
From SCL falling edge crossing 30% of V
Any pulse narrower than the max spec is
suppressed.
SCL falling edge crossing 30% of V
SDA exits the 30% to 70% of V
SDA crossing 70% of V
condition, to SDA crossing 70% of V
the following START condition.
Measured at the 70% of V
crossing 70% of V
From SDA falling edge crossing 30% of V
SCL falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
window, to SCL rising edge crossing 30% of
V
From SCL rising edge crossing 70% of V
SDA entering the 30% to 70% of V
From SCL rising edge crossing 70% of V
SDA rising edge crossing 30% of V
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
From SDA rising edge to SCL falling edge. Both
crossing 70% of V
until SDA enters the 30% to 70% of V
window.
From 30% to 70% of V
From 70% to 30% of V
Total on-chip and off-chip
Maximum is determined by t
For Cb = 400pF, max is about 2kΩ~2.5kΩ.
For Cb = 40pF, max is about 15kΩ~20kΩ
Before START condition
After STOP condition
are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the
CC
ISL95811
TEST CONDITIONS
CC
CC
CC
.
.
.
CC
CC
CC
CC
CC
during a STOP
R
crossing.
crossing.
and t
CC
window.
CC
CC
CC
CC
F
CC
.
CC
.
window.
, until
.
CC
during
CC
CC
CC
CC
, to
to
,
to
(Note 18)
0.1 * Cb
0.1 * Cb
1300
1300
MIN
20 +
20 +
600
600
600
600
100
600
600
600
10
0
2
0
1
(Note 4)
TYP
12
(Note 18) UNITS
MAX
400
900
250
250
400
50
20
October 6, 2008
FN6759.1
kHz
kΩ
ms
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns