ISL96017 Intersil Corporation, ISL96017 Datasheet
ISL96017
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ISL96017 Summary of contents
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... PART NUMBER PART MARKING ISL96017WIRT8Z* (Note) 96017WIZ ISL96017UIRT8Z* (Note) 96017UIZ *Add "-TK" suffix for 1000 units tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 ...
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... GND Ground 6 SDA Open drain serial interface data input/output 7 SCL Open drain serial interface clock input 8 WP Hardware write protection pin. Active low. Prevents any “Write” operation to the device. 2 ISL96017 16kbit EEPROM POWER-UP, INTERFACE, AND CONTROL LOGIC DESCRIPTION FN8243.1 ...
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... V (Note 7, 13) Coefficient DNL (Note 2, 5) Differential Non-Linearity INL (Note 2, 6) Integral Non-Linearity 3 ISL96017 Thermal Information Thermal Resistance (Typical, Note TDFN Package 90(°C/W) Moisture Sensitivity (see Technical Brief TB363 .Level 2 Maximum Junction Temperature (Plastic Package .150°C Recommended Operating Conditions Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . -40° ...
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... START Condition Hold Time HD:STA t Input Data Setup Time SU:DAT t Input Data Hold Time HD:DAT t STOP Condition Setup Time SU:STO 4 ISL96017 TEST CONDITIONS U version - DCP Register set to 7F hex. Measured between R and R pins version - DCP Register set to 7F hex. Measured between R and R pins. ...
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... SU:STA t HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) 5 ISL96017 TEST CONDITIONS From SDA rising edge to SCL falling edge. Both crossing 70% of VDD From SCL falling edge crossing 30% of VDD, until SDA enters the 30% to 70% of VDD window From 30% to 70% of VDD ...
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... TAP POSITION (DECIMAL) FIGURE 1. WIPER RESISTANCE vs TAP POSITION FOR 10kΩ (W) 0 25°C 0.15 0.1 0.05 0 -0.05 -0.1 -0.15 -0 TAP POSITION (DECIMAL) FIGURE 3. INL vs TAP POSITION FOR 10kΩ (W) 6 ISL96017 0. 3.6V 0.1 DD 0.05 0 -0. 3.0V -0.1 DD -0.15 -0.2 -0.25 100 120 140 0.2 0.15 0 3.6V DD 0.05 -0.05 -0.1 -0. 3. ...
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... LSBs of the Data Byte must be all zeros. Writing to address 7FE hex and 7FF hex can be done in two Write operations, or one Write operation with two Data Bytes. See next sections for interface protocol description TABLE 1. ISL96017 MEMORY MAP Data Bits ...
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... SDA SCL SDA FIGURE 6. VALID DATA CHANGES, START AND STOP CONDITIONS 8 ISL96017 internal non-volatile write cycle. The device enters its standby state when the internal non-volatile write cycle is completed. An ACK, Acknowledge software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the SDA bus after transmitting eight bits ...
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... The WP pin has logic HIGH to perform any Write operation to the device. When WP is active (LOW) the device ignores Data Bytes of a Write operation, does not 9 ISL96017 1 HIGH IMPEDANCE respond to them with ACK, and instead, goes to its standby state waiting for a new START condition. ...
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... ADDRESS R ADDRESS WITH T BYTE R/Wb FIGURE 9. READ SEQUENCE Vdd=3.3V Vdd=3.3V Vdd=3.3V 0.1uF Rpu WP RH SCL RW SDA RL ISL96017 R1 LAST DATA BYTE TO WRITE TO WRITE READ FIRST READ LAST READ K DATA BYTE DATA BYTE Vcc 0.1uF Vout ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 ISL96017 L8.3x3A 2X 0.15 ...