ISL97651 Intersil Corporation, ISL97651 Datasheet - Page 17

• Manufacturer Part Number: ISL97651
• Description: 4-Channel Integrated LCD Supply
• Manufacturer: Intersil Corporation

A
DELB pin is an open drain internal N-FET output used to
drive an external optional P-FET to provide a delayed A
supply which also has no initial pedistal voltage (see
Figure 15 and compare the A
curves). When the part is enabled, the N-FET is held off until
C
this period, the voltage potential of the source and gate of
the external P-FET (M0 in application diagram) should be
almost the same due to the presence of the resistor (R4)
NOTE: Not to scale
DLY
VDD_delay
reaches the 4th peak in the start-up sequence. During
Generation Using DELB
(A
VDD_delay
V
DELAYED
ON SLICE
V
V
V
BOOST
(A
BOOST
V
LOGIC
V
V
17
CDLY
VDD
VDD
V
REF
OFF
V
EN
ON
IN
)
)
and A
VDD_delayed
t
FIGURE 15. START-UP SEQUENCE
START-UP
START-UP SEQUENCE
TIMED BY C
VDD
t
VOFF
ISL97651
DLY
t
SS
across the source and gate, hence M0 will be off. Please
note that the maximum leakage of DELB in this period is
500nA. To avoid any mis-trigger, the maximum value of R4
should be less than:
Where V
threshold voltage of M0.
R
4_max
t
VON
<
GS(th)_min(M0)
V
------------------------------------------- -
GS th
(
500nA
)_min(M0)
OPERATION
NORMAL
t
VON-SLICE
is the minimum value of gate
PRESENT
FAULT
March 15, 2007
(EQ. 23)
FN7493.2