ISL98003 Intersil, ISL98003 Datasheet - Page 6

• Manufacturer Part Number: ISL98003
• Description: 8-Bit Video Analog Front End
• Manufacturer: Intersil

Timing Diagrams
Data Output Setup and Hold Timing
RGB Output Data Timing and Latency
YUV Output Data Timing and Latency
PIXEL DATA
R/G/B[7:0]
DATACLK
VIDEO IN
ANALOG
DATACLK
DATACLK
DATACLK
HSYNC
VIDEO IN
ANALOG
HSYNC
G[7:0]
R[7:0]
B[7:0]
HS
HS
OUT
OUT
IN
IN
P
P
0
0
6
P
P
1
1
8 DATACLK PIPELINE LATENCY
P
8 DATACLK PIPELINE LATENCY
P
2
2
THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED TO.
THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST OF THE
AFE’S OUTPUT SIGNALS
THE HSYNC EDGE (PROGRAMMABLE LEADING OR TRAILING) THAT THE DPLL IS LOCKED
TO. THE SAMPLING PHASE SETTING DETERMINES ITS RELATIVE POSITION TO THE REST
OF THE AFE’S OUTPUT SIGNALS
P
t
P
3
SETUP
3
P
WIDTH AND POLARITY
ISL98003
4
P
PROGRAMMABLE
4
t
HOLD
WIDTH AND POLARITY
P
5
PROGRAMMABLE
www.DataSheet.co.kr
P
5
P
6
P
6
P
7
P
7
P
8
P
G
B
8
0
0
(Y
(U
P
O
O
D
) G
) R
9
0
P
9
1
0
(Y
(V
P
1
0
10
) G
) B
D
1
P
10
2
2
(U
(Y
P
2
2
11
)
)
D
2
P
G
R
September 12, 2008
11
3
2
(V
(Y
P
2
3
12
)
)
D
3
P
FN6760.0
12
Datasheet pdf - http://www.DataSheet4U.net/