MB86941 Fujitsu Microelectronics, Inc., MB86941 Datasheet
MB86941
Related parts for MB86941
MB86941 Summary of contents
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... MB86941/942 DESCRIPTION MB86941 and MB86942 are dedicated peripheral LSIs for SPARClite*. The MB86941 and MB86942 are designed to enable compact configuration of high-performance systems with SPARClite architecture, and provide the following features SPARC is a registered trademark of SPARC International base on technology developed by Sun Microsystems, Inc ...
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... Generates read, write and data strobe signals according to the requirements of external devices. • SIO (Synchronous serial input/output) Simple synchronous type serial input/output • I/O port, 16-bit Individual direction control by bit 5V single power supply (MB86941), 3.3V single power supply (MB86942) Upward pin compatibility with MB86940C 2 ...
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... RS0 135 D12 136 D13 137 V 138 SS INDEX D14 139 D15 140 IRQ15 141 IRQ14 142 IRQ13 143 IRQ12 144 * : Only for MB86941. Open for MB86942. MB86941/942 (TOP VIEW) (FPT-144P-M03) 72 IPD0 71 CLK1 70 IN1 69 ACK1 68 PRSCK1 67 OUT1 OUT0 64 PRSCK0 ...
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... DSR1#, CTS1# SDTR1 RTS1#, DTR1# Serial Data TEMP1, TRDY1 Transmitter Receiver TRNDT1 TCLK1# RCLK1, RCVDT1 SYBRK1 RRDY1 * : Only for MB86941. Open for MB86942 Clock Clock Reset Internal Data Bus Internal Control Bus IRC Interrupt Request IRQ1 to IRQ15 Controller PRS0 ...
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... BIU (Bus Interface Unit) This block receives MPU (SPARClite) bus signals and bus controls signals (CLOCK, AS#, RD/WR#, CS#, ADR6 to ADR2, D<15:0>) and generates control signals for accessing MB86941/MB86942 internal resources. It also returns that Ready signal to the MPU which corresponds to the access time of each of such resources. ...
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... TEMP1 SDTR1 (12) TRDY1 TCLK1# RCVDT1 RCLK1 SYBRK1 RRDY1 (12) SS N.C.: (6/7) Note: Numerical value of a parenthesis shows numbers of PIN Only for MB86941. Open for MB86942. 6 IRQ15 to IRQ1 MB86941/2 ACK0 PRSCK0 CLK0 IN0 OUT0 ACK1 PRSCK1 CLK1 IN1 OUT1 CLK2 IN2 OUT2 ...
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... CS# pins determines which register is accessed. The RS5 pin has internal pull-down resistance (MB86941 only). Data ready output pin MB86941: Open drain output with 12mA “L” drive capability. Drives an “H” level signal for 3ns before going to High-Z state. MB86942: Normal output. READY2# signal deleted. If ...
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... MB86941/942 (Continued) Pin symbol I/O Pin no. D0 I/O 82 Data Bus 0 D1 I/O 83 Data Bus 1 D2 I/O 88 Data Bus 2 D3 I/O 89 Data Bus 3 D4 I/O 92 Data Bus 4 D5 I/O 93 Data Bus 5 D6 I/O 100 Data Bus 6 D7 I/O 101 Data Bus 7 D8 I/O 124 Data Bus 8 D9 I/O 125 Data Bus 9 D10 I/O 128 ...
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... Once an interrupt request is detected, it passes through priority control and masking control and is output at the IRL<3:0> pins as an interrupt request to the MPU. If these pins are not used, they should be fixed at inactive level. MB86941/942 Description and IRQ1 is lowest. 9 ...
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... MB86941/942 3. TIMER SIGNALS (16) Pin symbol I/O Pin no. CLK0 I 61 CLK0 : Timer Clock 0 IN0 I 62 CLK3 : Timer Clock 3 OUT0 O 65 CLK1 I 71 IN0 : Timer Input 0 IN1 I 70 IN3 : Timer Input 3 OUT1 O 67 CLK2 I 76 IN2 I 77 OUT0 : Timer Output 0 OUT2 O 79 CLK3 I 74 ...
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... Transmit Ready output pin When the CTS# signal is “L” and the command register is set to enable sending, these pins send an “H” level signal whenever the sending data buffer is empty. MB86941/942 Description (Continued) 11 ...
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... MB86941/942 Pin symbol I/O Pin no. TCLK0 Transmit Clock 0 TCLK1 Transmit Clock 1 RCVDT0 I 40 Receive Data 0 RCVDT1 I 50 Receive Data 1 RCLK0 I 34 Receive Clock 0 RCLK1 I 51 Receive Clock 1 12 Pin name Transmit Clock input pin In synchronous mode, the sending bit rate is fixed at the sending clock 1, so that the clock signal input at these pins becomes the sending bit rate ...
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... These pins are “H” level, when serial data received at the RCVDT0, RCVDT1 pins is converted to parallel data in the SDTR module and is in readable form. Then after the received data is read, these pins becomes “L” level at the end of the read signal. MB86941/942 Description 13 ...
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... When the input to the RCS# pins is “L”’ level, the input signal to these pins determines which of the external resource chip select signals CS0# to CS3# goes active. These pins have internal pull-up resistance (MB86941 only). This is the output pin for the ready signal generated by the module RCSTG. ...
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... SIO Interrupt Request Pin name Signal I/O port These pins may be used for input or output, as determined by register setting. These pins have internal pull-up resistance (MB86941 only). Pin name This is the input/output pin for the clock signal used for SIO serial data transfer. ...
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... V 81, 91, SS 102, 117, 127, 138 97, 108, 112, N.C. 115, 116, 123 (17 No. READY2# pin for MB86941. 16 Pin name Power supply input pin Grand pin These pins shall be used as an open pin. No also an open pin for MB86942. Description ...
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... – + maximum * – +120 –80 O Symbol MB86941 V 4. MB86941/942 Unit MB86942 –0.5 to +4. – –60 O Value Unit MB86942 3. ...
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... Symbol “H” level output V OH voltage “L” level output voltage V OL *1: MB86941 READY1#, READY2# *2: MB86941 D < > *3: MB86941 Other than READY1#, READY2# and D < > *4: MB86942 (3) Power Supply Current Parameter Symbol Power supply current (MB86941: V (MB86942: V ...
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... V IH Value Symbol Min. C — — OUT C / — MB86941: 1.5 V MB86942 PHL PLH MB86941 : 1.5 V MB86941: 1.5 V MB86942 MB86942 PZL PLZ MB86941: 1.5 V MB86942 0 PZH PHZ 0.5 V MB86941: 1.5 V MB86942 0.65 0. ...
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... Parameter Reset pulse width t : See “(2) Clock Signals.” CLK RESET Output MB86941 SW1 OFF ON OFF (MB86941: V (MB86942: V Symbol t RSTW t RSTW SW1 LSI tester SW2 Load capacitance MB86942 30 pF — SW2 OFF OFF ON ...
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... READY1#, READY2# output delay time READY1#, READY2# hold time D < > Output delay time at reading D < > Output hold time at reading D < > Input setup time at writing D < > Input hold time at writing * : READY2# is available for MB86941. (MB86941: V (MB86942: V MB86941 Symbol Min. ...
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... RWH RWS RD/WR RSH RSS RS < > High-Z READY1# MB86942: “H” level output READY2#* D < > at read High-Z t IDS D < > at write * : Only for MB86941 ASH t CSH t RWH t RSH t t RDYF RDYH t t ODD ODH t IDH High-Z MB86942: “ ...
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... RWH RWS RD/WR RSH RSS RS < > High-Z READY1# MB86942: “H” level output READY2#* D < > High-Z at read t IDS D < > at write * : Only for MB86941. t ASH t RDYF t ODD MB86941/942 t CSH t RWH t RSH t RDYH High-Z MB86942: “H” level output t ...
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... When the trigger mode is set for “L” level signal input or FALL-EDGE, a pulse of at least this width is received as a REQ-FF signal. Note that this rule does not guarantee that no interrupts less than this width will be received. IRQx 24 (MB86941: V (MB86942: V Symbol t IHW ...
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... IRQx clear setup time See “(2) Clock Signals.” CLK * : This parameter means the condition of REQUEST CLEAR execution and is applied at level trigger modes. IRQx (High Level Trigger) IRQx (Low Level Trigger) CLOCK AS# RD/WR# (MB86941: V (MB86942 3 Symbol Min IRQS CLK t IRQS REQ CLEAR ...
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... Parameter IRL < > clear delay time IRL < > mask delay time CLOCK AS# CS# RD/WR# RS < > High-Z READY1# MB86942: “H” level output READY2#* IRS < > Only for MB86941. 26 (MB86941: V (MB86942 Symbol Min. t — IRLCD t — IRLMD IRL clear ...
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... ACHW t 22 — ACLW t — 5 ACR t — 5 ACF t ACF t t ACLW ACHW t ACK (MB86941: V (MB86942: V Symbol t PSCLW t PSCHW t PSCLW t PSCHW (For t , see “(2) Clock Signals”) CLK , see “(5) Prescaler Timer Unit/Prescaler Input”) ACK t PSCHW MB86941/942 = +70 C) ...
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... INx (as IN pin of EVENT set ) • Timer output 1 Parameter OUT output delay time (for CLOCK) CLOCK OUTx 28 (MB86941: V (MB86942: V Symbol t TCKH t TCKL TCKL GS (MB86941: V (MB86942: V Symbol t OUTD1 t OUTD1 = 3 Value Unit Min. Max. 3 — ...
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... After setting to MODE1, write to RELOAD register/read COUNT register. • After setting to MODE3, write to RELOAD register. CLOCK AS# CS# RD/WR# Set to MODE, read count RS < > High-Z READY1# MB86942: “H” level output READY2#* OUTx * : Only for MB86941. MB86941/942 (MB86941 5 (MB86942 3 Value Symbol Min ...
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... Interval from register read to RRDY off t : See “(2) Clock Signals”. CLK CLOCK AS# CS# RS < > RD/WR# D < > High-Z READY1# MB86942: “H” level output READY2#* DSR# RRDY * : Only for MB86941. 30 (MB86941: V (MB86942 Symbol Min DSRS t 0 RRDYL Register read t DSRS ...
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... Delay time from register write to TRDY output t : See “(2) Clock Signals”. CLK CLOCK AS# CS# RS < > RD/WR# D < > READY1# High-Z READY2#* MB86942: “H” level output DSR#, RTS# TRDY * : Only for MB86941. MB86941/942 (MB86941 5 (MB86942 3 Value Symbol Min. Max ...
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... Command write cycle time (for initial value setup) Command write cycle time (for asynchronous mode) Command write cycle time (for synchronous mode See “(2) Clock Signals”. CLK CLOCK AS# CS# RD/WR# READY1# READY2 Only for MB86941. 32 (MB86941 5 (MB86942 3 Value Symbol Min ...
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... See “(2) Clock Signals”. CLK t TCKLW TCLK# ( 1/64 mode TCLK# ( 1/64 mode) t TCKLW TCLK mode, Sync mode) t TCKDT TRNDT (MB86941: V (MB86942: V Syncroh mode, 1 mode Symbol Min. Max — TCKHW t 14 — TCKLW t 0 100 TCKDT t TCKHW ...
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... Receive data hold time t : See “(2) Clock Signals”. CLK RCLK ( 1 mode, Sync mode) RCVDT t TCKDT RCLK ( 1/16 mode RCLK ( 1/64 mode) 34 (MB86941: V (MB86942: V Syncroh mode, 1 mode Symbol Min. Max — RCK t 12 — RCKHW t 7 — RCKLW t 6 — ...
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... See “(2) Clock Signals”. CLK MB86941/942 (MB86941 (MB86942 3 Value Symbol Min. Max BRKS t 10 BRKH t BRKH t BRKS (MB86941 (MB86942 3 Value Symbol Min. Max. t — TCKRDY t — TCKEMP t — RCKRDY t — SYCD1 t — ...
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... MB86941/942 36 ...
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... Control Signal Output Timing Parameter RCS# setup time RCS# hold time A < > setup time A < > hold time Delay time from RCS#, A1, A0 fix to CS3# to CS0# fix Delay time from CLOCK to RE#, WE#, DS# fix 40 (MB86941: V (MB86942 3 MB86941 Symbol Min. Max — ...
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... RCSS RCS# t ADS A < > CS3# to CS0# t ECSD RD/WR# DS# *1 RE# WE# “H” RDYOUT# RD/WR# DS# *2 RE# “H” WE# *2 RDYOUT# *1: Set register RTR0, RTR1. *2: Set register WTR0, WTR1. MB86941/942 * ECNTD t t ECNTD ECNTD * ECNTD ECNTD t RCSH t ADH t ECSD t ECNTD t ...
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... SICLK rise time SICLK fall time Setup time from SICLK rise/fall to valid SIRXD at receiving Delay time from SICLK rise/fall to SITXD output at Hold time from SICLK rise/fall to valid SITXD SICLK SICLK t SRD SIRXD SICLK SITXD 42 (MB86941: V (MB86942 Symbol t SCLKR t SCLKF t SRD t DTD transmitting ...
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... When the prescaler and timer are set to the following modes, the timer output signal OUT will not change at the anticipated time: Prescaler: External clock mode (PRESCALER REGISTER bit15 = “1”). Timer: Prescaler internal output signal used as operating clock, without using the external input pin (TCR bit 10 “10”). MB86941/942 43 ...
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... MB86941/942 REGISTER MAP RS5 Block to Register name RS0 name (HEX) TM0 00 (TRIGGER H MODE 0) TM1 01 (TRIGGER H MODE (REQ H SENSE) IRC RC 03 (REQ H CLEAR) MASK 04 H (MASK) IRL (IRL 05 H Latch/Clear Reserved Reserved 07 H SDR0 08 (SDTR H Data 0) SDTR 0 SCSR0 09 (SDTR H CM/ST 0) ...
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... CE CS OCONT IV TEST RELOAD VALUE COUNT VALUE — — — — — — — — — OCONT IV TEST RELOAD VALUE COUNT VALUE MB86941/942 MODE EVENT PRESCALE VALUE MODE EVENT — — — — — — — ...
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... MB86941/942 (Continued) RS5 Block to Register name RS0 name (HEX) PDR 20 (PORT H DATA) I/O PORT DCR (PORT 21 H DIRECTION Reserved Reserved 23 H SCR 24 (SERIAL H CONTROL) STR 25 (SERIAL H STATUS) RDR SIO 26 (RECEIVE H DATA) TDR 27 (TRANSMIT H DATA) TRR 28 (TRANSFER H RATE Reserved 2A Reserved H 2B ...
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... ORDERING INFORMATION Part number MB86941PFV MB86942PFV Package 144-pin Plastic QFP (FPT-144P-M03) 144-pin Plastic QFP (FPT-144P-M03) MB86941/942 Remarks 47 ...
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... MB86941/942 PACKAGE DIMENSION 144-pin Plastic QFP (FPT-144P-M03) 22.60±0.20(.890±.008)SQ 20.00±0.10(.787±.004)SQ 108 109 INDEX 144 "A" LEAD No. 1 0.50(.0197)TYP 0.10(.004) 1995 FUJITSU LIMITED F144003S-2C 3.85(.152)MAX (Mounting height) 0.05(.002)MIN 73 (STAND OFF) 72 17.50 (.689) REF 37 36 0.20±0.10 0.125±0.05 ...
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... Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9812 FUJITSU LIMITED Printed in Japan MB86941/942 All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use ...