MB86941 Fujitsu Microelectronics, Inc., MB86941 Datasheet - Page 7

• Manufacturer Part Number: MB86941
• Description: Peripheral Lsi For Sparclite
• Manufacturer: Fujitsu Microelectronics, Inc.

1. MPU INTERFACE SIGNALS (34/33)
RESET#
CLOCK
AS#
RD/WR#
CS#
RS0
RS1
RS2
RS3
RS4
RS5
READY1#
READY2#
WSEL
Pin symbol
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
Pin no.
118
119
120
121
122
135
134
132
131
130
133
113
20
17
Reset
Clock
Address Strobe
Read/Write
Chip Select
Register Select 0
Register Select 1
Register Select 2
Register Select 3
Register Select 4
Register Select 5
Ready 1
Ready 2
Wait Select
Pin name
Reset input pin
Input an “L” signal to this pin to reset the chip.
System clock input pin
The chip contains some modules that use the clock
signal from this pin (not divided), and other modules
that use the clock signal divided in half.
Address strobe input pin
Input an “L” signal to this pin to determine register
access according to the signals input to the RS<5:0>,
CS#, and RD/WR# pins.
Read/write input pin
Input an “H” signal to designate a read cycle, or an “L”
signal to designate a write cycle.
Chip select input pin
Register select input pin
The combination of input signals to the RS<5:0> and
CS# pins determines which register is accessed.
The RS5 pin has internal pull-down resistance
(MB86941 only).
Data ready output pin
MB86941: Open drain output with 12mA “L” drive
MB86942: Normal output. READY2# signal deleted. If
Wait select input pin
Input to this pin determines the interface timing with
the MPU.
Fix “L” to set register read/write access to 3 cycles, or
fix “H” to set register read/write access to 2 cycles.
This pin has internal pull-up resistance (MB86941
only).
Clock not divided: BIU, RCSTG, IP
Clock divided: IRC, PRS0, PRS1, TM0 to TM3,
capability. Drives an “H” level signal for 3ns
before going to High-Z state.
the READY generator circuit in the MPU is
used, it is not necessary to connect this pin
to the MPU.
SDTR0, SDTR1, SIO
Description
MB86941/942
(Continued)
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