DG201 Intersil Corporation, DG201 Datasheet - Page 4
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DG201
Manufacturer Part Number
DG201
Description
CMOS Quad SPST Analog Switch
Manufacturer
Intersil Corporation
Datasheet
1.DG201.pdf
(7 pages)
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Test Circuits
Typical Applications
Using the V
The DG201 has an internal voltage divider setting the TTL
threshold on the input control lines for V+ equal to +15V. The
schematic shown in Figure 4 with nominal resistor values,
gives approximately 2.4V on the V
signal goes from +0.8V to +2.4V, Q
turn the switch ON and OFF. If the power supply voltage is
less than +15V, then a resistor (R
between V+ and the V
The table shows the value of this resistor for various supply
voltages, to maintain TTL compatibility. If CMOS logic levels
with a +5V supply are being used, the threshold shifts are
less critical, but a separate column of suitable values is given
in the table. For logic swings of -5V to + 5V, no resistor is
needed.
In general, the “low” logic level should be <0.8V to prevent
Q
incorrect switch function).
1
V+ SUPPLY (V)
3V
0V
and Q
LOGIC
INPUT
+15
+12
+10
+9
+8
+7
2
FIGURE 1. t
from both being ON together (this will cause
REF
Terminal
R
REF
ON
LEVELS (k )
EXT
AND t
TABLE 1.
pin, to restore +2.4V at V
420
190
136
FOR TTL
98
70
-
4
OFF
EXT
REF
1
TEST CIRCUIT
and Q
3V
) must be added
INPUT 10V
LOGIC
INPUT
ANALOG
pin. As the TTL input
10pF
R
2
EXT
LEVELS (k )
switch states to
FIGURE 3. OFF ISOLATION TEST CIRCUIT
FOR CMOS
136
98
70
-
-
-
REF
V
1k
OUT
.
DG201
ANALOG INPUT
100
2V
P-P
AT 1MHz
V
OUT
3V
0V
FIGURE 2. CHARGE INJECTION TEST CIRCUIT
LOGIC
Q
INPUT
INPUT
1
51
V+
PROTECTION
RESISTOR
FIGURE 4.
118k
23k
GATE
V
REF
INPUT 10V
ANALOG
10nF
R
EXT
Q
2
V
OUT