74F273 Fairchild, 74F273 Datasheet
74F273
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74F273 Summary of contents
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... Octal D-Type Flip-Flop General Description The 74F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transi- tion, is transferred to the corresponding flip-flop’ ...
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... LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition X Immaterial LOW-to-HIGH clock transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com U.L. Description HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 50/33 ...
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... Recognized as a LOW Signal Min Min Min Max V 2.7V IN Max V 7.0V IN Max V V OUT 0.0 All other pins grounded V 150 mV IOD 0.0 All other pins grounded Max V 0.5V IN Max OUT CP Max D MR HIGH n www.fairchildsemi.com ...
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... Hold Time, HIGH or LOW H t (L) Data (L) MR Pulse Width, LOW W t (H) CP Pulse Width W t (L) HIGH or LOW W t Recovery Time REC www.fairchildsemi.com 125 5. Min Typ Max Min ...
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... Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20B Package Number M20D 5 www.fairchildsemi.com ...
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... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. ...