74F899 Fairchild, 74F899 Datasheet - Page 3

• Manufacturer Part Number: 74F899
• Description: 9-Bit Latchable Transceiver with Parity Generator/Checker
• Manufacturer: Fairchild

Function Table
H
Note 1: O/E
Functional Block Diagram
GAB
HIGH Voltage Level
H
H
H
H
H
H
L
L
L
L
L
GBA
ODD/EVEN
H
H
H
H
H
H
L
L
L
L
L
Inputs
SEL LEA LEB
X
H
H
H
H
L
L
L
L
L
L
X
H
X
X
H
H
H
H
H
L
L
L
LOW Voltage Level
X
H
H
H
H
H
X
H
L
L
L
Busses A and B are 3-STATE.
Generates parity from B[0:7] based on O/E (Note 1). Generated parity
Generated parity checked against BPAR and output as ERRB.
Generates parity from B[0:7] based on O/E. Generated parity
parity checked against BPAR and output as ERRB. Generated parity also fed back
through the A latch for generate/check as ERRA.
Generates parity from B latch data based on O/E. Generated parity
Generated parity checked against latched BPAR and output as ERRB.
BPAR/B[0:7]
BPAR and output as ERRB.
BPAR/B[0:7]
Feed-through mode. Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check as ERRA.
Generates parity for A[0:7] based on O/E. Generated parity
checked against APAR and output as ERRA.
Generates parity from A[0:7] based on O/E. Generated parity
parity checked against APAR and output as ERRA. Generated parity also fed back
through the B latch for generate/check as ERRB.
Generates parity from A latch data based on O/E. Generated parity
Generated parity checked against latched APAR and output as ERRA.
APAR/A[0:7]
Feed-through mode. Generated parity checked against APAR and output as ERRA.
APAR/A[0:7]
Feed-through mode. Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check as ERRB.
APAR/A0:7] Feed-through mode. Generated parity checked against
APAR/A[0:7]
BPAR/B[0:7]
BPAR/B[0:7]
X
Immaterial
3
Operation
BPAR. Generated parity
APAR. Generated
BPAR. Generated
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APAR.
BPAR.
APAR.