MACH445-12 Lattice, MACH445-12 Datasheet
MACH445-12
Related parts for MACH445-12
MACH445-12 Summary of contents
Page 1
... FINAL COM’L: -12/15/20 MACH445-12/15/20 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS 100-pin version of the MACH435 in PQFP 5 V, in-circuit programmable JTAG, IEEE 1149.1 JTAG testing capability 128 macrocells MHz f CNT 70 inputs with pull-up resistors 64 outputs 192 flip-flops — 128 macrocell flip-flops — ...
Page 2
... Clock Generator 2 I2, I5 Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE Input Switch Input Switch Matrix Matrix OE CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4 MACH445-12/15/20 OE Clock Generator OE Clock Generator OE Clock Generator OE Clock Generator 17468E-1 ...
Page 3
... I = Input I/O = Input/Output VCC = Supply Voltage PQFP BLOCK A BLOCK H (83) (12) (13) (14) (15) (16) (17) (18) (19) (20) (23) (24) (25) (26) (27) (28) (29) (30) (31) BLOCK D BLOCK E MACH445-12/15/20 80 GND 79 GND TD0 78 TRST* 77 I/O55 76 (73) I/O54 75 (72) I/O53 74 (71) I/O52 73 (70) I/O51 72 (69) 71 I/O50 (68) I/O49 70 (67) I/O48 69 (66) I4/CLK3 ...
Page 4
... The Valid Combinations table lists configurations planned to be supported in volume for this device. Con- YC sult your local sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. MACH445-12/15/20 OPTIONAL PROCESSING Blank = Shipped in Trays OPERATING CONDITIONS C = Commercial ( +70 C) PACKAGE TYPE ...
Page 5
... Emulating all flip-flop types with a D-type flip-flop is also made possible. Register type emulation is automatically handled by the design software. Table 1 illustrates which product term clusters are available to each macrocell within a PAL block. Refer to Figure 1 for cluster and macrocell numbers. MACH445-12/15/20 5 ...
Page 6
... JTAG is the commonly used acronym for the IEEE Standard 1149.1–1990. The JTAG standard defines input and output pins, logic control functions, and instructions. Lattice/Vantis has incorporated this stan- dard into the MACH445 device. The JTAG standard was developed as a means of providing both board-level and device-level testing. MACH445-12/15/20 ...
Page 7
... MACH435 device. This feature facilitates doing worst-case designs for which data is loaded from sources which have low (or zero) minimum output propagation delays from clock edges. MACH445-12/15/20 7 ...
Page 8
... M6 C7 Macrocell M7 C8 Macrocell M8 C9 Macrocell M9 C10 Macrocell M10 C11 M11 Macrocell C12 Macrocell M12 C13 Macrocell M13 C14 Macrocell M14 C15 Macrocell M15 16 16 Figure 1. MACH445 PAL Block MACH445-12/15/ I/O0 I/O Cell I/O I/O1 Cell I/O I/O2 Cell I/O3 I/O Cell I/O I/O4 Cell M9 M10 ...
Page 9
... 5 =25 MHz Test Conditions MHz OUT and I (or I and OZL IH OZH MACH445-12 (Com’l) ) Operating + with +4. +5.25 V Min Typ = Min 2.4 2.0 – mA) 255 OUT = 25 C (Note 5) A Typ = 5 ...
Page 10
... Global Gate Width LOW (for LOW transparent) GWS or HIGH (for HIGH transparent) t Input Register Clock to Combinatorial Output ICO 10 External Feedback Internal Feedback (f ) CNTA No Feedback (Note 3) External Feedback Internal Feedback (f ) CNTS No Feedback (Note 3) MACH445-12 (Com’l) -12 Min Max Unit D-type 5 ns T-type ...
Page 11
... Transparent Input Latch to Product Term Output t Setup Time from Input, I/O, or Feedback Through SLLS Transparent Input Latch to Output Gate t Input, I/O, or Feedback to Output Through Transparent PDLL Input and Output Latches 1/( WICL WICH Gate MACH445-12 (Com’l) -12 Min Max Unit D-type 9 ns T-type 10 ns LOW 6 ns HIGH ...
Page 12
... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 12 Gate MACH445-12 (Com’l) -12 Min Max Unit ...
Page 13
... OUT CC f =25 MHz (Note 5) A Test Conditions MHz OUT and I (or I and OZL IH OZH MACH445-15/20 (Com’l) ) Operating + with +4. +5.25 V Min Typ Max 2.4 0.5 2.0 0.8 10 –100 10 –100 –30 –160 255 Typ = 25 C, ...
Page 14
... WHA D-type 10 T-type LOW 6 HIGH 6 D-type COS T-type 47.6 D-type 66.6 ) CNTS T-type 62.5 1/( WLS WHS 83 MACH445-15/20 (Com’l) -20 Max Min Max Unit 31.2 MHz 30.3 MHz 37 MHz 35.7 MHz 41.7 MHz ...
Page 15
... Input and Output Latches -15 Min D-type 15 T-type 16 LOW 6 HIGH 6 1/( 83.3 WICL WICH Disable (Note Gate 12 MACH445-15/20 (Com’l) -20 Max Min Max Unit 62.5 MHz ...
Page 16
... These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where frequency may be affected. 4. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. 16 -15 Min Gate 18 MACH445-15/20 (Com’l) -20 Max Min Max Unit ...
Page 17
... Output, LOW I (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH I (mA –2 – –20 –40 –60 –80 –100 Input MACH445-12/15/ 1.0 17468E (V) OH 17468E 17468E-6 17 ...
Page 18
... The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register Frequency (MHz) MACH445-12/15/20 MACH445 17468E-7 ...
Page 19
... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air MACH445-12/15/20 Typ PQFP Unit 5 C/W ...
Page 20
... Gate t WL 17468E- Registered Input t HIR Input V T Register Clock t ICO V T Output Register Clock 17468E-13 MACH445-12/15/ 17468E PDL Latched Output (MACH 2, 3, and GWS Gate Width (MACH 2, 3, and ICS ...
Page 21
... Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical SIL HIL Latched Input (MACH 2 and 4) t IGOL Latched Input and Output (MACH 2, 3, and 4) MACH445-12/15/ IGO V T 17468E-15 t PDLL SLL ...
Page 22
... Gate t WICL 17468E-17 Input, I/ Feedback Registered V T Output t ARR Clock V T 17468E- Outputs + V OL Output Disable/Enable MACH445-12/15/20 t WIGL Input Latch Gate Width (MACH 2 and 4) t APW Asynchronous Preset 0. 0.5V 17468E- 17468E- APR ...
Page 23
... Apply Output Commercial 300 390 5 pF MACH445-12/15/20 OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL Test Point 17468E-22 Measured ...
Page 24
... All frequencies except f MAX other measured AC parameters. f ured directly. ” (SECOND CHIP MACH445-12/15/ type is the mini- MAX + t ). Usually, this minimum feedback.” MAX . Because this involves no MAXIR + the sum of SIR HIR + t ). The clock widths are nor- ...
Page 25
... Min Pattern Data Retention Time Max Reprogramming Cycles bipolar parts result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Min Units 10 Years 20 Years 100 Cycles MACH445-12/15/20 Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions 25 ...
Page 26
... INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection Input 100 k Preload Feedback Circuitry Input I/O MACH445-12/15/20 CC 100 17468E-24 ...
Page 27
... Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform MACH445-12/15/20 can rise to its steady state, two CC rise must be monotonic. Max 10 See Switching Characteristics V CC ...
Page 28
... All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support Preload Off Mode Figure 2. Preload/Reset Conflict Set Reset Figure 3. Combinatorial Latch MACH445-12/15/20 Preloaded HIGH Preloaded HIGH 17468E-26 17468E-27 ...