T35L6432A-5T Taiwan Memory Technology, Inc., T35L6432A-5T Datasheet - Page 5

• Manufacturer Part Number: T35L6432A-5T
• Description: 64K x 32 SRAM
• Manufacturer: Taiwan Memory Technology, Inc.

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INTERLEAVED BURST ADDRESS TABLE (MODE = NC/VCC)
LINEAR BURST ADDRESS TABLE (MODE = GND)
PARTIAL TRUTH TABLE FOR READ/WRITE
WRITE PASS-THROUGH TRUTH TABLE
Note: 1. Previous cycle may be any cycle(non-burst, burst, or wait).
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
Initiate WRITE cycle, one bytes ONE L 2 No new cycle
Function
READ
READ
WRITE one byte
WRITE all byte
WRITE all byte
Address= A(n-1), data= D(n-1)
Address= A(n-1), data= D(n-1)
Address= A(n-1), data= D(n-1)
Address= A(n-1), data= D(n-1)
Initiate WRITE cycle, all bytes All L 2,3 Initiate READ cycle
Initiate WRITE cycle, all bytes All L 2,3 No new cycle
Initiate WRITE cycle, all bytes All L 2,3 No new cycle
First Address
First Address
2.
3.
(external)
(external)
OPERATION
A...A00
A...A01
A...A10
A...A11
A...A00
A...A01
A...A10
A...A11
BWE
GW
PREVIOUS CYCLE
CH
TE
= LOW yields the same result for all-byte WRITE operation.
is LOW for individual byte WRITE.
GW
H
H
H
H
L
Second Address
Second Address
(internal)
(internal)
BWn
A...A01
A...A00
A...A11
A...A10
A...A01
A...A10
A...A11
A...A00
BWE
Register A(n), Q= D(n-1)
Q = D(n-1)
Q = HIGH-Z
Q = D(n-1) for one byte
H
X
L
L
L
OPERATION
PRESENT CYCLE
BW1
P. 5
X
H
L
L
X
Third Address
Third Address
(internal)
(internal)
A...A10
A...A11
A...A00
A...A01
A...A10
A...A11
A...A00
A...A01
BW2
CE
X
H
H
X
L
H
H
H
L
BWn
H
H
H
H
Publication Date: DEC. 1998
OE
BW3
H No carry-over from
L Read D(n)
L No carry-over from
L No carry-over from
X
H
H
X
L
Fourth Address
Fourth Address
previous cycle
previous cycle
previous cycle
T35L6432A
(internal)
(internal)
NEXT CYCLE
OPERATION
A...A11
A...A10
A...A01
A...A00
A...A11
A...A00
A...A01
A...A10
Revision:A
BW4
X
H
H
X
L