ST16C552 Exar Corporation, ST16C552 Datasheet
ST16C552
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ST16C552 Summary of contents
Page 1
... INTP interrupt. The INTP interrupt is active high (logic 1) on the ST16C552 whereas INTP is active low (logic 0) on the ST16C552A part when the interrupt latch mode is selected. The 552/552A is fabricated in an advanced CMOS process with power down mode to reduce the power consumption. The 552A does not support the power down mode ...
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... ST16C552/552A Figure 1, Block Diagram D0-D7 -IOR -IOW -RESET BIDEN A0-A2 -CSA -CSB -CSP INT A,B INTP -RXRDY -TXRDY Rev. 3.40 Transmit Transmit FIFO Shift Registers Register Receive Receive FIFO Shift Registers Register Printer Data Ports Printer Control Logic Modem Control Clock Logic & Baud Rate ...
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... CPU data transfers. I/O Data Bus (Bi-directional) - These pins are the eight bit, three state data bus for transferring information to or from the controlling CPU the least significant bit and the first data bit in a transmit or receive serial data stream. 3 ST16C552/552A Pin Description ...
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... The difference between the ST16C552 and ST16C552A is the output state of INTP. INTP is active high (logic 1) on the ST16C552 whereas INTP is active low (logic 0) on the ST16C552A part when the interrupt latch mode is selected. I Interrupt Select mode - This pin selects the interrupt type for the printer port (-INTP) ...
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... Master Reset (active low logic 0 on this pin will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. (See ST16C552/552A External Reset Conditions for initialization details.) O Receive Ready A/B (active low). This function is associated with the dual channel UARTs and provide the RX FIFO/ RHR status for individual receive channels (A-B) ...
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... ST16C552/552A SYMBOL DESCRIPTION Symbol Pin SLCT 65 -SLCTIN 58 -STROBE 55 -TXRDY A/B 22,42 VCC 23,40,64 -CD A/B 29,8 -CTS A/B 28,13 Rev. 3.40 Signal Type reached. I Select (with internal pull-up) - General purpose input or line printer select status. Normally this pin is connected to a printer output (active low) that indicates the ready status of a printer, i.e., on-line and/or on-line and ready. ...
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... Receive Data Input, RX A-B. - These inputs are associated with individual serial channel(s) to the 552. The RX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the RX input pins are disabled and TX data is internally connected to the 7 ST16C552/552A Pin Description ...
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... The 552/552A is available in two versions, the ST16C552 and the ST16C552A. The 552A provides a active low (logic 0) interrupt for the printer port (INTP) while the 552 provides an active high (logic 1) INTP interrupt ...
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... MSR), programmable data rate (clock) control registers (DLL/DLM), and a user assessable scratchpad register (SPR). The printer port registers functions data holding Rev. 3.40 ST16C552/552A registers (PR), I/O status register (SR), I/O select register (IOSEL), and a command and control register (COM/CON). Register functions are more fully de- scribed in the following paragraphs ...
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... ST16C552/552A Table 4, INTERNAL REGISTER DECODE READ MODE General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): Note Receive Holding Register Interrupt Status Register Line Status Register Modem Status Register Scratchpad Register ...
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... Figure 4, Receive Time-out Interrupt). The actual time out value is T (Time out length in bits Rev. 3.40 ST16C552/552A P (Programmed word length) + 12. To convert the time out value to a character value, the user has to consider the complete word length, including data information length, start bit, parity bit, and the size of stop bit, i ...
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... ST16C552/552A same system design. The rate table is configured via the DLL and DLM internal register functions. Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections of baud rate generator. Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB) provides a user capability Table 5, BAUD RATE GENERATOR PROGRAMMING TABLE (1 ...
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... The transmitter output (TX) and the receiver input (RX) are disconnected from their associated interface pins, and instead are connected Rev. 3.40 ST16C552/552A together internally (See Figure 6). The -CTS, -DSR, -CD, and -RI are disconnected from their normal modem control inputs pins, and instead are connected inter- nally to -DTR, -RTS, INT enable and MCR bit-2 ...
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... ST16C552/552A Figure 6, INTERNAL LOOP-BACK MODE DIAGRAM D0-D7 -IOR -IOW -RESET BIDEN A0-A2 -CSA -CSB -CSP INT A,B INTP -RXRDY -TXRDY Rev. 3.40 Transmit Transmit FIFO Shift Registers Register Receive Receive FIFO Shift Registers Register Printer Data Ports Printer Control Logic Clock & Baud Rate Generator ...
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... Input mode 1 Note don’t care Rev. 3.40 ST16C552/552A input and/or output functions. The signals have internal pull-up resistors and can be wire-or’d. Normally, - STROBE is used to strobe PD0-PD7 bus data into a printer input buffer. -SLCTIN normally selects the printer while AutoFDXT signals the printer to auto-linefeed. ...
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... ST16C552/552A REGISTER FUNCTIONAL DESCRIPTIONS The following table delineates the assigned bit functions for the eighteen 552/552A internal registers. The assigned bit functions are more fully defined in the following paragraphs. Table 7, ST16C552/552A INTERNAL REGISTERS Register BIT-7 [Default] Note 5* General Register Set: Note 1* ...
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... THR empty flag in the LSR register will be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR. Note that a write operation can be performed when the transmit holding register empty flag is set (logic 0 = FIFO full, logic 1= at least Rev. 3.40 ST16C552/552A BIT-6 BIT-5 BIT-4 BIT-3 bit-6 ...
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... Not Used - initialized to a logic 0. IER BIT-5: (ST16C552 only) Logic 0 = Disable the power down mode. (normal default condition). The ST16C552A does not support the power down mode and this bit is set to “0”. Logic 1 = Enable the power down mode (MCR bit-7 must also be a logic 1 before power down will be activated) ...
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... FIFO counter logic (the receive shift regis- ter is not cleared or altered). This bit will return to a logic 0 after clearing the FIFO. Rev. 3.40 ST16C552/552A FCR BIT-2: Logic FIFO transmit reset. (normal default condition) Logic 1 = Clears the contents of the transmit FIFO and resets the FIFO counter logic (the transmit shift regis- ter is not cleared or altered) ...
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... ST16C552/552A FCR BIT 4-5: Not Used - initialized to a logic 0. FCR BIT 6-7: (logic 0 or cleared is the default condi- tion, RX trigger level = 1) These bits are used to set the trigger level for the receive FIFO interrupt. An interrupt is generated when the number of charac- ters in the FIFO equals the programmed trigger level. ...
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... LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit is forced to a logical 1 for the transmit and receive data. 5 LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit 6 is forced to a logical 0 for the transmit and receive 7 data ST16C552/552A Word length Stop bit length (Bit time(s)) 5,6,7 1-1/2 6,7,8 2 ...
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... ST16C552/552A LCR LCR LCR Parity selection Bit-5 Bit-4 Bit parity Odd parity Even parity Force parity odd parity Forced even parity LCR BIT-6: When enabled the Break control bit causes a break condition to be transmitted (the TX output is forced to a logic 0 state) ...
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... LSR BIT-7: Logic Error. (normal default condition) Logic least one parity error, framing error or Rev. 3.40 ST16C552/552A break indication is in the current FIFO data. This bit is cleared when RHR register is read. Modem Status Register (MSR) This register provides the current state of the control interface signals from the modem, or other peripheral device that the 552/552A is connected to ...
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... MCR bit-3 in the MCR register. Note: Whenever any MSR bit 0-3: is set to logic “1”, a MODEM Status Interrupt will be generated. Scratchpad Register (SPR) The ST16C552/552A provides a temporary data reg- ister to store 8 bits of user information. PRINTER PORT REGISTER DESCRIPTIONS Port Register (PR) ...
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... This bit allows the state of -INTP to be read back by the external CPU. Logic 0 = Interrupt (-INTP output) is disabled (normal default condition) Rev. 3.40 ST16C552/552A Logic 1 = Interrupt (-INTP output) is enabled COM BIT 5-7: Not Used - initialized to a logic 1. Control Register (CON) This register provides control of the printer port output logical states and controls the printer interrupts INIT and -INTP ...
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... Logic 0 + BIDEN 1 = PD7-PD0 are set for output mode (normal default condition) Logic 1 + BIDEN 1 = PD7-PD0 are set for input mode CON BIT 6-7: Not Used - initialized to a logic 1. Rev. 3.40 ST16C552/552A EXTERNAL RESET CONDITION REGISTERS RESET STATE (UART) IER BITS 0-7=0 ISR ISR BIT-0=1, ISR BITS 1-7=0 ...
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... PD7 - PD0 setup time 40s T PD7 - PD0 hold time 41h T Delay from -ACK low to interrupt low 42d T Delay from -IOR to reset interrupt 43d T Reset pulse width R N Baud rate devisor Rev. 3.40 ST16C552/552A Limits Limits 3.3 5.0 Min Max Min Max ...
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... ST16C552/552A ABSOLUTE MAXIMUM RATINGS Supply range Voltage at any pin Operating temperature Storage temperature Package dissipation DC ELECTRICAL CHARACTERISTICS (-40 - +85 C for Industrial grade packages), Vcc=2.97 - 5.5V unless otherwise specified. A Symbol Parameter V Clock input low level ILCK V Clock and printer port input high level ...
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... General read timing Valid T7h A ctive ctive General write timing 29 ST16C552/552A Add r ess Valid T7h ...
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... ST16C552/552A T2w EXTERNAL CLOCK -IOW Active -RTS Change of state -DTR -CD -CTS -DSR INT -IOR -RI Rev. 3.40 T1w T3w External clock timing T17d Change of state Change of state T18d Active T19d Active Modem input/output timing 30 EX-CK-1 Change of state T18d Active Active Active Active T18d Change of state ...
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... START BIT RX INT -IOR Rev. 3.40 ST16C552/552A DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK Receive timing 31 STOP BIT D6 D7 PARITY NEXT BIT DATA START BIT T20d Active T21d Active X552-RX-1 ...
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... ST16C552/552A START BIT RX -RXRDY -IOR Receive ready timing in none FIFO mode Rev. 3.40 DATA BITS (5- STOP BIT D6 D7 PARITY NEXT BIT DATA START BIT T25d Active Data Ready T26d Active X552-RX-2 ...
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... START BIT RX -RXRDY -IOR Rev. 3.40 ST16C552/552A DATA BITS (5- Receive timing in FIFO mode 33 STOP BIT D6 D7 PARITY First byte BIT that reaches the trigger level T25d Active Data Ready T26d Active X552-RX-3 ...
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... ST16C552/552A START BIT TX INT -IOW Active Rev. 3.40 DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS T23d 16 BAUD RATE CLOCK Transmit timing 34 STOP BIT PARITY NEXT BIT DATA START BIT T22d Active Tx Ready T24d Active X552-TX-1 ...
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... START BIT TX -IOW Active D0-D7 BYTE #1 -TXRDY Transmit ready timing in none FIFO mode Rev. 3.40 ST16C552/552A DATA BITS (5- T27d Active Transmitter ready 35 STOP BIT D6 D7 PARITY NEXT BIT DATA START BIT T28d Transmitter not ready X552-TX-2 ...
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... ST16C552/552A START BIT TX -IOW Active D0-D7 BYTE #16 T27d -TXRDY Transmit ready timing in FIFO mode Rev. 3.40 DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS T28d FIFO Full 36 STOP BIT D6 D7 PARITY BIT X552-TX-3 ...
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... T40d INTP -IOR T40s NORMAL MODE INTSEL PD0-PD7 Rev. 3.40 T39w INTERRUPT LATCHED MODE SELECT T41h VALID DATA Printer port timing (552 only) 37 ST16C552/552A T42d T43d X552-PR-1 ...
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... ST16C552/552A -ACK T40d INTP -IOR T40s NORMAL MODE INTSEL PD0-PD7 Rev. 3.40 T39w INTERRUPT LATCHED MODE SELECT T41h VALID DATA Printer port timing (552A only) 38 T42d T43d X552-PR-2 ...
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... EXAR Corporation is adequately protected under the circumstances. Copyright 2003 EXAR Corporation Datasheet September 2003 Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com Reproduction, in part or whole, without prior written consent of EXAR Corporation is prohibited. Rev. 3.40 ST16C552/552A CHANGES NOTICE 39 DATE Dec 2003 ...