ST16C552 Exar Corporation, ST16C552 Datasheet - Page 16

• Manufacturer Part Number: ST16C552
• Description: DUAL UART WITH 16-BYTE FIFO AND PARALLEL PRINTER PORT
• Manufacturer: Exar Corporation

ST16C552/552A
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the eighteen 552/552A internal registers. The
assigned bit functions are more fully defined in the following paragraphs.
Rev. 3.40
A2 A1 A0
0
0
0
0
0
0
1
1
1
1
0
0
Table 7, ST16C552/552A INTERNAL REGISTERS
General Register Set: Note 1*
Special Register Set: Note *2
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
1
0
1
0
1
0
1
RHR [XX]
MSR [X0]
THR [XX]
MCR [00]
SPR [FF]
DLM [XX]
Register
[Default]
FCR [00]
LCR [00]
DLL [XX]
LSR [60]
IER [00]
ISR [01]
Note 5*
enabled
FIFO’s
RCVR
trigger
(MSB)
divisor
enable
BIT-7
bit-15
down
FIFO
latch
error
bit-7
bit-7
data
bit-7
bit-7
Pwr
CD
0
enabled
FIFO’s
THR &
RCVR
trigger
empty
BIT-6
(LSB)
bit-14
break
TSR
bit-6
bit-6
bit-6
bit-6
set
RI
0
0
empty
BIT-5
mode
bit-13
down
parity
THR.
DSR
bit-5
bit-5
bit-5
bit-5
Pwr
En
set
0
0
0
16
interrupt
BIT-4
break
bit-12
parity
even
back
CTS
bit-4
bit-4
loop
bit-4
bit-4
0
0
0
Interrupt
INT A/B
framing
Modem
priority
enable
enable
Status
select
BIT-3
mode
bit-11
DMA
parity
delta
bit-3
bit-3
bit-2
error
bit-3
bit-3
-CD
INT
interrupt
Receive
Status
priority
BIT-2
XMIT
bit-10
FIFO
parity
reset
delta
bit-2
bit-2
bit-1
error
bit-2
bit-2
Line
stop
INT
bits
-RI
[X]
Transmit
Register
interrupt
Holding
overrun
RCVR
priority
length
BIT-1
-RTS
-DSR
FIFO
reset
word
error
delta
bit-1
bit-1
bit-0
bit-1
bit-1
bit-1
bit-9
INT
Register
Receive
Holding
receive
enable
status
length
BIT-0
-DTR
ready
-CTS
FIFO
word
delta
bit-0
bit-0
bit-0
bit-0
bit-0
bit-8
data
INT