IDT70T633 Integrated Device Technology, IDT70T633 Datasheet - Page 13

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IDT70T633

Manufacturer Part Number
IDT70T633
Description
512k X 18, 3.3v/2.5v Dual-port Ram, Interleaved I/o
Manufacturer
Integrated Device Technology
Datasheet

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Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
Timing Waveform of Write Cycle No. 2, CE Controlled Timing
CE or SEM
NOTES:
1. R/W or CE or UB or LB = V
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM = V
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
8. If OE = V
9. To access RAM, CE = V
ADDRESS
CE or SEM
ADDRESS
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
DATA
(Figure 1).
placed on the bus for the required t
specified t
DATA
DATA
and CE
WR
UB, LB
UB, LB
is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
R/W
R/W
OUT
OE
IN
IN
1
= V
(9)
(9)
(9)
IL
WP
(9)
during R/W controlled write cycle, the write pulse width must be the larger of t
.
IH
. CE = V
IL
IH
transition occurs simultaneously with or after the R/W = V
IL
when CE
and SEM = V
IH
during all address transitions.
t
AS
DW
0
EW
t
(6)
AS
= V
. If OE = V
or t
(6)
IH
IH
WP
. To access semaphore, CE = V
and/or CE
(4)
) of a CE = V
IH
during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
1
= V
t
WZ
IL
IL
.
(7)
t
and a R/W = V
t
AW
AW
t
t
WC
WC
t
t
EW
WP
(2)
(2)
IH
13
IL
and SEM = V
for memory array writing cycle.
IL
transition, the outputs remain in the High-impedance state.
t
t
DW
DW
IL
WP
. t
EW
or (t
must be met for either condition. CE = V
t
WR
WZ
Industrial and Commercial Temperature Ranges
(3)
+ t
DW
t
t
DH
t
DH
WR
) to allow the I/O drivers to turn off and data to be
t
OW
(3)
(7)
t
HZ
(7)
(1,5,8)
(4)
(1,5,8)
IL
when CE
5670 drw 11
5670 drw 10
0
= V
IL
.
.
.

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