IDT70T633 Integrated Device Technology, IDT70T633 Datasheet - Page 18

• Manufacturer Part Number: IDT70T633
• Description: 512k X 18, 3.3v/2.5v Dual-port Ram, Interleaved I/o
• Manufacturer: Integrated Device Technology

Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V
NOTES:
1. To ensure that the earlier of the two ports wins. t
2. CE
3. OE = V
4. If M/S = V
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY (M/S = V
NOTES:
1. t
2. BUSY is asserted on port "B" blocking R/W
3. t
DATA
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
DATA
WH
WB
ADDR
ADDR
BUSY
0L
R/W
must be met for both BUSY input (SLAVE) and output (MASTER).
only applies to the slave mode.
OUT "B"
= CE
IN "A"
IL
for the reading port.
"A"
"A"
"B"
"B"
IL
0R
(slave), BUSY is an input. Then for this example BUSY
= V
IL
; CE
t
APS
1L
= CE
(1)
BUSY
1R
R/W
R/W
= V
IH
"A"
"B"
"B"
.
"B"
, until BUSY
APS
is ignored for M/S = V
"B"
t
goes HIGH.
WB
(3)
t
"A"
BAA
= V
MATCH
IH
IL
t
and BUSY
18
WC
(SLAVE).
t
WP
(2)
"B"
t
WP
input is shown above.
Industrial and Commercial Temperature Ranges
MATCH
IL
t
DW
t
WDD
)
VALID
t
WH
(1)
5670 drw 15
t
DDD
(3)
.
t
BDA
t
DH
IH
5670 drw 14
t
)
BDD
VALID
(2,4,5)
.