IDT72V295 Integrated Device Technology, IDT72V295 Datasheet - Page 14

• Manufacturer Part Number: IDT72V295
• Description: 128k X 18 Supersync Fifo, 3.3v
• Manufacturer: Integrated Device Technology

mode, OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG ( PAF )
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D - m) words are written
to the FIFO. The PAF will go LOW after (131,072-m) writes for the IDT72V295
and (262,144-m) writes for the IDT72V2105. The offset “m” is the full offset
value. The default setting for this value is stated in the footnote of Table 1.
IDT72V295 and (262,145-m) writes for the IDT72V2105, where m is the full
offset value. The default setting for this value is stated in the footnote of
Table 2.
and FWFT Mode), for the relevant timing information.
PROGRAMMABLE ALMOST-EMPTY FLAG ( PAE )
FIFO reaches the almost-empty condition. In IDT Standard mode, PAE will
go LOW when there are n words or less in the FIFO. The offset “n” is the empty
offset value. The default setting for this value is stated in the footnote of Table 1.
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
In IDT Standard mode, EF is a double register-buffered output. In FWFT
In FWFT mode, the PAF will go LOW after (131,073-m) writes for the
See Figure 16, Programmable Almost-Full Flag Timing (IDT Standard
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
PAF is synchronous and updated on the rising edge of WCLK.
The Programmable Almost-Empty flag (PAE) will go LOW when the
EF/OR is synchronous and updated on the rising edge of RCLK.
TM
131,072 x 18, 262,144 x 18
14
in the FIFO. The default setting for this value is stated in the footnote of Table 2.
dard and FWFT Mode), for the relevant timing information.
HALF-FULL FLAG ( HF )
FIFO beyond half-full sets HF LOW. The flag remains LOW until the
difference between the write and read pointers becomes less than or equal
to half of the total depth of the device; the rising RCLK edge that accom-
plishes this condition sets HF HIGH.
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 131,072
for the IDT72V295 and 262,144 for the IDT72V2105.
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 131,073 for the
IDT72V295 and 262,145 for the IDT72V2105.
for the relevant timing information. Because HF is updated by both RCLK
and WCLK, it is considered asynchronous.
DATA OUTPUTS ( Q
See Figure 17, Programmable Almost-Empty Flag Timing (IDT Stan-
In FWFT mode, the PAE will go LOW when there are n+1 words or less
PAE is synchronous and updated on the rising edge of RCLK.
This output indicates a half-full FIFO. The rising WCLK edge that fills the
In IDT Standard mode, if no reads are performed after reset (MRS or
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
See Figure 18, Half-Full Flag Timing (IDT Standard and FWFT Modes),
(Q
0
- Q
17
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
) are data outputs for 18-bit wide data.
0
-Q
17
)