IDT72V3650 Integrated Device Technology, IDT72V3650 Datasheet - Page 33

• Manufacturer Part Number: IDT72V3650
• Description: 2k X 36 Supersync Ii Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTE:
1. X = 9 for the IDT72V3640, X = 10 for the IDT72V3650, X = 11 for the IDT72V3660, X = 12 for the IDT72V3670, X = 13 for the IDT72V3680 and X = 14 for the IDT72V3690.
NOTES:
1. If the part is empty at the point of Retransmit, the output ready flag (OR) will be updated based on RCLK (Retransmit clock cycle), valid data will also appear on the output.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
3. OE = LOW.
4. W
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
6. RM is set LOW during MRS.
Q
IDT72V3640/50/60/70/80/90 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36 and 32,768 x 36
WCLK
WCLK
RCLK
0
D = 1,025 for the IDT72V3640, 2,049 for the IDT72V3650, 4,097 for the IDT72V3660, 8,193 for the IDT72V3670, 16,385 for the IDT72V3680 and 32,769 for the IDT72V3690.
WEN
SEN
REN
- Q
PAE
PAF
1
LD
OR
, W
HF
SI
RT
n
2
, W
t
ENS
3
= first, second and third words written to the FIFO after Master Reset.
W
x
Figure 15. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
BIT 0
t
t
t
ENS
LDS
DS
t
ENS
t
W
RTS
x+1
t
t
ENH
LDH
Figure 14. Zero Latency Retransmit Timing (FWFT Mode)
1
t
A
EMPTY OFFSET
t
t
ENH
HF
t
SKEW2
1
W1
2
t
PAFS
2
t
A
BIT X
TM
33
36-BIT FIFO
(1)
W
BIT 0
2
(4)
3
t
A
t
PAES
FULL OFFSET
W
3
(4)
COMMERCIAL AND INDUSTRIAL
t
4
A
TEMPERATURE RANGES
BIT X
t
ENH
t
t
W
LDH
DH
4
(1)
(4)
APRIL 6, 2006
5
t
A
4667 drw20
4667 drw19
t
ENH
W
5