IDT72V261LA Integrated Device Technology, IDT72V261LA Datasheet - Page 21

• Manufacturer Part Number: IDT72V261LA
• Description: 3.3 Volt Cmos Supersync Fifo
• Manufacturer: Integrated Device Technology

NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
3. OE = LOW.
4. W
5. OR goes LOW at 60 ns + 2 RCLK cycles + t
NOTE:
1. X = 13 for the IDT72V261LA and X = 14 for the IDT72V271LA.
Q
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
WCLK
WCLK
RCLK
D = 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA.
0
SEN
WEN
REN
- Q
PAE
PAF
1
LD
, W
OR
SI
RT
HF
n
2
, W
t
3
ENS
= first, second and third words written to the FIFO after Master Reset.
W
x
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENH
BIT 0
t
t
t
ENS
LDS
DS
t
ENS
t
RTS
t
RTS
REF
.
t
t
ENH
LDH
EMPTY OFFSET
t
t
REF
t
ENH
HF
t
SKEW2
Figure 12. Retransmit Timing (FWFT Mode)
1
2
t
PAF
1
W
x+1
BIT X
21
(1)
BIT 0
2
t
PAE
FULL OFFSET
COMMERCIAL AND INDUSTRIAL
3
t
A
t
ENH
t
REF
TEMPERATURE RANGES
(5)
W
1
(4)
BIT X
t
t
t
LDH
LDH
ENH
t
DH
(1)
W
4
2
t
A
4673 drw 16
4673 drw 15
t
ENH
W
3