IDT72V261LA Integrated Device Technology, IDT72V261LA Datasheet - Page 9

• Manufacturer Part Number: IDT72V261LA
• Description: 3.3 Volt Cmos Supersync Fifo
• Manufacturer: Integrated Device Technology

NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
LD
0
0
0
X
1
1
1
8
8
8
8
IDT72V261LA ' 16,384 x 9 *+BIT
WEN
5
5
X
0
1
1
1
0
1
7
7
3FFH if LD is HIGH at Master Reset
3FFH if LD is HIGH at Master Reset
07FH if LD is LOW at Master Reset
07FH if LD is LOW at Master Reset
EMPTY OFFSET (MSB) REG.
EMPTY OFFSET (LSB) REG.
FULL OFFSET (LSB) REG.
FULL OFFSET (MSB) REG.
REN
X
1
0
1
1
0
1
DEFAULT VALUE
DEFAULT VALUE
Figure 4. Programmable Flag Offset Programming Sequence
00H
00H
Figure 3. Offset Register Location and Default Values
SEN
1
1
X
X
X
1
0
WCLK
X
X
X
X
0
0
0
0
9
8
8
8
8
IDT72V271LA ' 32,768 x 9 * BIT
RCLK
X
X
X
X
X
6
6
7
7
3FFH if LD is HIGH at Master Reset
3FFH if LD is HIGH at Master Reset
07FH if LD is LOW at Master Reset
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Serial shift into registers:
28 bits for the 72V261LA
30 bits for the 72V271LA
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
No Operation
Write Memory
Read Memory
No Operation
07FH if LD is LOW at Master Reset
Ending with Full Offset (MSB)
EMPTY OFFSET (LSB) REG.
FULL OFFSET (LSB) REG.
EMPTY OFFSET (MSB) REG.
FULL OFFSET (MSB) REG.
DEFAULT VALUE
DEFAULT VALUE
COMMERCIAL AND INDUSTRIAL
00H
00H
Selection
TEMPERATURE RANGES
4673 drw 06
0
0
0
0
4673 drw 07