IDT72V70190 Integrated Device Technology, IDT72V70190 Datasheet - Page 6

• Manufacturer Part Number: IDT72V70190
• Description: 3.3 Volt Time Slot Interchange Digital Switch 256 X 256
• Manufacturer: Integrated Device Technology

CONNECTION MEMORY CONTROL
of the CCO bit of each connection memory location are output on the CCO pin
once every frame. The contents of the CCO bits of the connection memory are
transmitted sequentially on to the CCO pin (2 bit cells for each bit in connection
memory) and are synchronous with the data rates on the other serial streams.
The CCO bit is output one channel before the corresponding channel on the
serial streams.
location controls the output drivers-enables (if high) or disables (if low). See
Table 4 for detail.
Processor Mode and Connection Mode. If high, the contents of the connection
memory are output on the TX streams. If low, the stream address bit (SAB) and
the channel address bit (CAB) of the connection memory defines the source
information (stream and channel) of the time-slot that will be switched to the output
from data memory.
The Control Register is only accessed when A7-A0
are all zeroed. When A7 =1, up to 32 bytes are
randomly accessable via A0-A4 at any one instant.
Of which stream these bytes (channels) are accessed
is determined by the state of CR b 2 -CR b 0.
IDT72V70190 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 256 x 256
The CCO pin is a 4.096 Mb/s output, which carries 512 bits. The contents
If the ODE pin or the OSB bit is high, the OE bit of each connection memory
The processor channel (PC) bit of the connection memory selects between
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
Channel 0
10000000
Control Register
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
Channel 1
10000001
Connection Memory
Data Memory
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
Channel 2
10000010
CR
b
7
CR
Figure 3. Addressing Internal Memories
b
CR
6 CR
1
0
b
4
b
5 CR
6
allows the per-channel selection between variable and constant throughput
delay modes.
looped back to the RX input channel (i.e., RX n channel m data comes from the
TX n channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero.
INITIALIZATION OF THE IDT72V70190
the outputs should be put in high impedance by holding the ODE low. While the
ODE is low, the microprocessor can initialize the device, program the active
paths, and disable unused outputs by programming the OE bit in connection
memory. Once the device is configured, the ODE pin (or OSB bit depending
on initialization) can be switched.
b
4 CR
10011111
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
Channel 31
The V/C (Variable/Constant Delay) bit in each connection memory location
If the LPBK bit is high, the associated TX output channel data is internally
After power up, the state of the connection memory is unknown. As such,
b
3 CR
b
2 CR
External Address Bits A7-A0
b
COMMERCIAL TEMPERATURE RANGE
1 CR
CR
0
0
0
0
1
1
1
1
b
2 CR
b
0
0
0
1
1
0
0
1
1
b
1 CR
0
1
0
1
0
1
0
1
b
0
Stream
5717 drw03
0
1
2
3
4
5
6
7