IDT72V70190 Integrated Device Technology, IDT72V70190 Datasheet - Page 9

• Manufacturer Part Number: IDT72V70190
• Description: 3.3 Volt Time Slot Interchange Digital Switch 256 X 256
• Manufacturer: Integrated Device Technology

TABLE 7 — FRAME ALIGNMENT REGISTER (FAR) BITS
IDT72V70190 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 256 x 256
15-13
10-0
Bit
12
11
Read/Write Address:
Reset Value:
15
0
Unused
CFE
(Complete Frame Evaluation)
FD11
(Frame Delay Bit 11)
FD10-0
(Frame Delay Bits)
ST-BUS
14
0
Offset Value
Offset Value
GCI Frame

FE Input
FE Input
Name
Frame
13
0
CLK
CLK
CFE
02
0000
12
H
.
H
.
FD11 FD10
11
0
0
The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1)
Must be zero for normal operation.
When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment
offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0.
or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.
The binary value expressed in these bits refers to the measured input offset value. These bits are rest to
zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
1
1
10
Figure 4. Example for Frame Alignment Measurement
2
2
FD9
9
3
3
4
FD8
4
8
5
5
FD7
(FD[10:0] = 06
(FD11 = 0, sample at CLK LOW phase)
7
6
6
9
7
7
FD6
6
8
8
H
(FD[10:0] = 09
(FD11 = 1, sample at CLK HIGH phase)
)
Description
FD5
5
9
9
10
10
FD4
4
H
11
11
)
FD3
12
12
COMMERCIAL TEMPERATURE RANGE
3
13
13
FD2
2
14
14
5717 drw04
15
FD1
15
1
16
FD0
0