82C55A Intersil Corporation, 82C55A Datasheet - Page 2

• Manufacturer Part Number: 82C55A
• Description: CMOS Programmable Peripheral Interface
• Manufacturer: Intersil Corporation

Pin Description
Functional Diagram
SYMBOL
PC0-PC7
PA0-PA7
PB0-PB7
RESET
D0-D7
A0-A1
GND
V
WR
CS
RD
CC
SUPPLIES
BI-DIRECTIONAL
POWER
RESET
D7-D0
DATA BUS
WR
RD
CS
A1
A0
1-4, 37-40
NUMBER
27-34
18-25
10-17
PIN
8, 9
26
35
36
7
6
5
DATA BUS
CONTROL
BUFFER
+5V
GND
WRITE
LOGIC
READ
TYPE
I/O
I/O
I/O
I/O
I
I
I
I
I
V
recommended for decoupling.
GROUND
DATA BUS: The Data Bus lines are bidirectional three-state pins connected to the
system data bus.
RESET: A high on this input clears the control register and all ports (A, B, C) are set
to the input mode with the “Bus Hold” circuitry turned on.
CHIP SELECT: Chip select is an active low input used to enable the 82C55A onto the
Data Bus for CPU communications.
READ: Read is an active low input control signal used by the CPU to read status
information or data via the data bus.
WRITE: Write is an active low input control signal used by the CPU to load control
words and data into the 82C55A.
ADDRESS: These input signals, in conjunction with the RD and WR inputs, control
the selection of one of the three ports or the control word register. A0 and A1 are
normally connected to the least significant bits of the Address Bus A0, A1.
PORT A: 8-bit input and output port. Both bus hold high and bus hold low circuitry are
present on this port.
PORT B: 8-bit input and output port. Bus hold high circuitry is present on this port.
PORT C: 8-bit input and output port. Bus hold circuitry is present on this port.
CC
CONTROL
CONTROL
GROUP A
GROUP B
: The +5V power supply pin. A 0.1 F capacitor between pins 26 and 7 is
82C55A
INTERNAL
DATA BUS
2
8-BIT
DESCRIPTION
GROUP A
GROUP A
GROUP B
GROUP B
PORT A
PORT C
PORT B
UPPER
PORT C
LOWER
(8)
(4)
(8)
(4)
PC7-PC4
PC3-PC0
PB7-PB0
PA7-PA0
I/O
I/O
I/O
I/O