V4070 EM Microelectronic, V4070 Datasheet - Page 6

• Manufacturer Part Number: V4070
• Description: Crypto Contactless Identification Device
• Manufacturer: EM Microelectronic

Authentication
In this mode the chip first receives the 56 bits of ran-
dom number followed by seven bits of divergency bits
that the reader should send as “0” followed by 28 Bits
of cipher_1 (f(RN)) as authentication of the lock. The
chip decides if the authentication is accepted. In this
case the V4070 sends a header (12 manchester coded
‘1’s followed by 4 manchester coded ‘0’s). Next 20
Bits of cipher_2 (g(RN)) are sent. Else it sends a sin-
gle NAK.
Upon completion of this command the V4070 returns
to Standby Mode.
Write Word
The Write Word command is followed by the address
and data. The address consists of a 5 bit block con-
taining 4 data bits and 1 even parity. The data con-
sists of 4 times 5 bit blocks, each block consisting of 4
data bits and 1 associated even parity bit. One addi-
tional block consists of 4 column parity bits and a trail-
ing zero (refer to fig 10).
OUTPUT
D15 D14 D13 D12 P3 D11 D10 D09 D08 P2 D07 D06 D05 D04 P1 D03 D02 D01 D00 P0
Authentication
INPUT
First bit recieved
LIW
RM
EM MICROELECTRONIC-MARIN SA
Command
PC3 PC2 PC1 PC0 "0"
RN
A3 A2 A1 A0 Padd
Address
“0000000”
Tdiv
Data
f(RN)
Figure 10
Tauth
Header
After reception of the write command, the address and
the data, the V4070 will check the parity and the Lock-
Bits. If all the conditions are fullfilled, an Acknowledge
pattern (ACK) will be issued, and the EEPROM writ-
ing process will start. At the end of programming the
chip will send an Acknowledge pattern (ACK). If at least
one of the checks fails, the chip will issue a No Ac-
knowledge pattern (NAK) instead of ACK and return
to the Standby Mode.
The V4070 might also return to the Standby Mode with-
out sending back a NAK if the incomming data is cor-
rupted and/or inconsistent.
g(RN)
Divergency
Receive
(28 Bits)
Receive
(56 Bits)
Begin
f(RN)
RN
First bit input
Column Even Parity
LIW
Word Organisation
D15
D11
D07
D03
PC3
D14
D10
D06
D02
PC2
D13
D09
D05
D01
PC1
(20 Bits)
header
valid?
Send
g(RN)
Send
f(RN)
End
Data
D12
D08
D04
D00
PC0
Y
Row Even Parity
P3
P2
P1
P0
0
N
Last bit input
logic "0"
V4070
Send
NAK
Figure 11
Figure 8
Figure 9
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