T6819 ATMEL Corporation, T6819 Datasheet - Page 4

• Manufacturer Part Number: T6819
• Description: (T6819 / T6829) Dual Triple DMOS Output Driver
• Manufacturer: ATMEL Corporation

Functional Description
Serial Interface
4
T6819/T6829
Data transfer starts with the falling edge of the CS signal. Data must appear at DI syn-
chronized to CLK and are accepted on the falling edge of the CLK signal. LSB (bit 0,
SRR) has to be transferred first. Execution of new input data is enabled on the rising
edge of the CS signal. When CS is high, Pin DO is in tristate condition. This output is
enabled on the falling edge of CS. Output data will change their state with the rising
edge of CLK and stay stable until the next rising edge of CLK appears. LSB (bit 0, TP) is
transferred first.
Figure 3. Data Transfer
Input Data Protocol
CLK
DO
Bit
CS
10
11
12
13
14
15
DI
0
1
2
3
4
5
6
7
8
9
Input Register
SRR
0
TP
1
S1L
LS1
SRR
OLD
OCS
HS1
HS2
HS3
PH1
PH2
PH3
LS1
LS2
LS3
PL1
PL2
PL3
SI
S1H
HS1
2
3
S2L
LS2
Status register reset (high = reset; the bits PSF and OVL in the
output data register are set to low)
Controls output LS1 (high = switch output LS1 on)
Controls output HS1 (high = switch output HS1 on)
See LS1
See HS1
See LS1
See HS1
Output LS1 additionally controlled by PWM Input
Output HS1 additionally controlled by PWM Input
See PL1
See PH1
See PL1
See PH1
Open load detection (low = on)
Overcurrent shutdown (high = overcurrent shutdown is active)
Software inhibit; low = standby, high = normal operation
(data transfer is not affected by standby function because the
digital part is still powered)
Function
S2H
4
HS2
5
S3L
LS3
6
S3H
HS3
n. u.
7
PL1
8
n. u.
PH1
9
n. u.
PL2
10
n. u.
PH2
11
n. u.
PL3
12
n. u.
PH3
13
OVL
OLD
4531A–BCD–10/02
14
OCS
INH
15
PSF
SI