T6819 ATMEL Corporation, T6819 Datasheet - Page 5

• Manufacturer Part Number: T6819
• Description: (T6819 / T6829) Dual Triple DMOS Output Driver
• Manufacturer: ATMEL Corporation

After power-on reset, the input register has the following status
The following patterns are used to enable internal test modes of the IC. It is not recommended to use these patterns during
normal operation.
4531A–BCD–10/02
Bit 15
Bit 15
H
H
H
H
SI
Bit 14
Bit 14
H
H
H
OCS
H
(OCS)
Bit 13
Bit 13
H
H
H
OLD
H
Bit 12
Bit 12
PH3
H
L
L
L
Bit 11
Bit 11
H
PL3
L
L
Output Data Protocol
L
Bit
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
Bit 10
Bit 10
H
PH2
L
L
L
Output (Status)
Status HS1
Status HS2
Status HS3
Status LS1
Status LS2
Status LS3
Register
Bit 9
Bit 9
H
PL2
L
L
n. u.
n. u.
n. u.
n. u.
n. u.
n. u.
OVL
PSF
L
INH
TP
Bit 8
Bit 8
PH1
H
L
L
L
Function
Temperature prewarning: high = warning
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off); not affected by SRR
Normal operation: high = output is on, low = output is off
Open-load detection: high = open load, low = no open load
(correct load condition is detected if the corresponding output is
switched off); not affected by SRR
Description see LS1
Description see HS1
Description see LS1
Description see HS1
Not used
Not used
Not used
Not used
Not used
Not used
Over-load detected: set high, when at least one output is
switched off by a short-circuit condition or an overtemperature
event. Bits 1 to 6 can be used to detect the affected switch.
(open-load detection bit OLD = high)
Inhibit: this bit is controlled by software (bit SI in input register)
High = standby, low = normal operation
Power-supply fail: undervoltage at Pin VS detected
Bit 7
Bit 7
H
PL1
L
L
L
(HS3)
Bit 6
Bit 6
HS3
L
L
L
L
(LS3)
Bit 5
Bit 5
LS3
L
L
L
L
(HS2)
Bit 4
Bit 4
HS2
L
L
L
L
(LS2)
Bit 3
Bit 3
LS2
L
L
L
L
T6819/T6829
(HS1)
Bit 2
Bit 2
HS1
L
L
L
L
(LS1)
Bit 1
Bit 1
L
L
L
LS1
L
(SRR)
Bit 0
SRR
Bit 0
L
L
L
L
5