ICL7104 Intersil, ICL7104 Datasheet - Page 15

• Manufacturer Part Number: ICL7104
• Description: 14-Bit/16-Bit/ Microprocessor- Compatible/ 2-Chip/ A/D Converter
• Manufacturer: Intersil

Detailed Description
DIGITAL SECTION
The digital section includes the clock oscillator circuit, a
16-bit or 14-bit binary counter with output latches and TTL-
compatible three-state output drivers, polarity, over-range
and control logic and UART handshake logic, as shown in
the Block Diagram Figure 9 (16-bit version shown).
Throughout this description, logic levels will be referred to as
“low” or “high”. The actual logic levels are defined under
“ICL7104 Electrical Specification”. For minimum power con-
sumption, all inputs should swing from GND (low) to V+
(high). Inputs driven from TTL gates should have 3 - 5k
pullup resistors added for maximum noise immunity.
MODE Input
The MODE input is used to control the output mode of the
converter. When the MODE pin is connected to GND or left
open (this input is provided with a pulldown resistor to
ICL7104-16 POL
ICL7104-14
SECTION
ANALOG
HBEN
TO
O/R
COMP OUT
AZ
INT
DEINT(+)
DEINT(-)
POL
B16
INITIAL
CLEAR
TABLE 5. THREE-STATE BYTE FORMATS AND ENABLE PINS
B15
O/R
ICL8052/ICL7104, ICL8068/ICL7104
STATUS
CONVERSION
B14
B14
CONTROL
2
LOGIC
B13
B13
FIGURE 9. DIGITAL SECTION
MBEN
HBEN
R/H
26
B12
B12
CLOCK
18/16 THREE-STATE OUTPUTS
B11
B11
(1)
5-20
24
OSCILLATOR
AND CLOCK
CIRCUITRY
ensure a low level when the pin is left open), the converter is
in its “Direct” output mode, where the output data is directly
accessible under the control of the chip and byte enable
inputs. When the MODE input is pulsed high, the converter
enters the UART handshake mode and outputs the data in
three bytes for the 7104-16 or two bytes for the 7104-14 then
returns to “direct” mode. When the MODE input is left high,
the converter will output data in the handshake mode at the
end of every conversion cycle. (See section entitled “Hand-
shake Mode” for further details).
STATUS Output
During a conversion cycle, the STATUS output goes high at
the beginning of Input Integrate (Phase II), and goes low
one-half clock period after new data from the conversion has
been stored in the output latches. See Figure 8 for details of
this timing. This signal may be used as a “data valid” flag
(data never changes while STATUS is low) to drive inter-
rupts, or for monitoring the status of the converter.
CLOCK
18/16 LATCHES
B10
B10
18/16 BIT COUNTER
(2)
CE/LD
23
CLOCK
B9
B9
LATCH
CLOCK
(3)
25
B8
B8
MODE
HANDSHAKE
B7
B7
21
LOGIC
B6
B6
SEND
27
B5
B5
LBEN
LBEN
B4
B4
HBEN
(-16 ONLY)
CE/LD
MBEN
LBEN
B3
B3
B2
B2
B1
B1