MCP3202-BIST Microchip Technology, MCP3202-BIST Datasheet - Page 15

• Manufacturer Part Number: MCP3202-BIST
• Description: 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface
• Manufacturer: Microchip Technology

6.0
6.1
With most microcontroller SPI ports, it is required to
send groups of eight bits. It is also required that the
microcontroller SPI port be configured to clock out data
on the falling edge of clock and latch data in on the rising
edge. Depending on how communication routines are
used, it is very possible that the number of clocks
required for communication will not be a multiple of eight.
Therefore, it may be necessary for the MCU to send
more clocks than are actually required. This is usually
done by sending ‘leading zeros’ before the start bit,
which are ignored by the device. As an example,
Figure 6-1 and Figure 6-2 show how the MCP3202 can
be interfaced to a MCU with a hardware SPI port.
Figure 6-1 depicts the operation shown in SPI Mode 0,0,
FIGURE 6-1:
FIGURE 6-2:
MCU Transmitted Data
X = Don’t Care Bits
(Aligned with falling
1999 Microchip Technology Inc.
X = Don’t Care Bits
edge of clock)
MCU Received Data
(Aligned with rising
SCLK
SCLK
D
D
MCU Received Data
MCU Transmitted Data
(Aligned with rising
edge of clock)
OUT
OUT
D
(Aligned with falling
D
CS
CS
edge of clock)
IN
IN
edge of clock)
APPLICATIONS INFORMATION
Using the MCP3202 with
Microcontroller (MCU) SPI Ports
MCU latches data from A/D Converter
on rising edges of SCLK
MCU latches data from A/D Converter
on rising edges of SCLK
SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).
SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).
0
1
1
X
X
Data stored into MCU receive register
Data stored into MCU receive register
X
0
2
2
after transmission of first 8 bits
X
after transmission of first 8 bits
X
X
0
3
3
X
X
X
0
4
HI-Z
4
HI-Z
X
X
X
0
5
5
X
X
X
0
6
6
X
X
X
0
Data is clocked out of
A/D Converter on falling edges
A/D Converter on falling edges
7
Data is clocked out of
7
X
X
Start
Start
X
Bit
1
8
Start
X
Start
X
8
1
Bit
SGL/
DIFF
SGL/
DIFF
9
9
X
X
Preliminary
ODD/
SIGN
SGL/
DIFF
Data stored into MCU receive register
Data stored into MCU receive register
after transmission of second 8 bits
after transmission of second 8 bits
10
10
X
X
MSBF
ODD/
SIGN
11
11
X
X
MSBF
NULL
NULL
BIT
BIT
X
12
12
(Null)
(Null)
0
0
B11
X
B11
X
which requires that the SCLK from the MCU idles in the
‘low’ state, while Figure 6-2 shows the similar case of
SPI Mode 1,1 where the clock idles in the ‘high’ state.
As shown in Figure 6-1, the first byte transmitted to the
A/D Converter contains seven leading zeros before the
start bit. Arranging the leading zeros this way produces
the output 12 bits to fall in positions easily manipulated
by the MCU. The MSB is clocked out of the A/D Con-
verter on the falling edge of clock number 12. After the
second eight clocks have been sent to the device, the
MCU receive buffer will contain three unknown bits (the
output is at high impedance until the null bit is clocked
out), the null bit and the highest order four bits of the
conversion. After the third byte has been sent to the
device, the receive register will contain the lowest order
eight bits of the conversion results. Easier manipulation
of the converted data can be obtained by using this
method.
13
13
B11
B11
B10
X
B10
X
14
14
B10
B10
X
B9
B9
X
15
15
B9
B9
X
X
B8
16
B8
B8
B8
16
X
B7
B7
X
Don’t Care
17
17
Don’t Care
B7
B7
Data stored into MCU receive register
Data stored into MCU receive register
X
X
B6
B6
18
18
after transmission of last 8 bits
after transmission of last 8 bits
B6
B6
X
X
B5
B5
19
19
B5
B5
X
X
B4
B4
20
20
MCP3202
B4
B4
X
X
B3
B3
21
21
B3
B3
X
X
B2
B2
22
22
DS21034A-page 15
B2
B2
X
X
B1
B1
23
23
B1
B1
X
X
B0
B0
24
24
B0
B0
X