TDA8961 Philips Semiconductors, TDA8961 Datasheet - Page 16

• Manufacturer Part Number: TDA8961
• Description: ATSC/NTSC digital TV front-end chipset
• Manufacturer: Philips Semiconductors

Philips Semiconductors
Pins PDO0 to PDO7 and PDOCLK are normally part of the
transport stream output interface. The signals to these
pins are normally routed via an internal multiplexer.
However, in the ITU656 bypass mode, these pins connect
directly to the lower 8 bits of ADIN9 to ADIN0 and ADCLK.
In this mode, PDOSYNC and PDOVAL are kept LOW and
the polarity of PDOERR depends on the setting of I
bit FPBP. If required, these transport stream interface
outputs can be forced to 3-state mode by making I
bit TSO = 0 (see Table 14).
ITU656 bypass mode is enabled by setting the
I
S
The TDA8961 transport stream output interface is able to
calculate the Segment Error, or packet error, Rate (SER)
over a certain time period. The time period can be set to
either 1, 4, 8 or 16 seconds by the I
(see Table 14). The IC counts any packet errors occurring
in the set time period. At the end of the time period, the
16-bit value representing the counted number of packet
errors can be read via I
After a reset, the register value is set to 12935 (3287H)
which is equivalent to an infinite SER. The TDA8961 is
able to automatically reset itself when the SER exceeds a
preset threshold value. The SER threshold is a 14-bit value
programmable in the range 3 to 13000 represented by
I
It should be noted that the time period set by the
SERTM bits should be long enough to allow this threshold
to be reached. This reset function is enabled by setting
I
disabled by default.
Boundary scan interface
The TDA8961 TAP conforms to the IEEE 1149.1 (JTAG)
standard. It is used for board-level testing and for internally
testing integrated circuits. The JTAG standard defines the
on-chip test logic which comprises an instruction register,
a group of test data registers including a bypass register
and a boundary scan register, four dedicated pins
comprising the TAP, and a TAP controller.
2000 May 19
2
2
2
C-bus TSMODE bits to 10.
EGMENT ERROR COUNTER
C-bus bits SER_THRES (see Table 14).
C-bus bit SER_RST (see Table 14). The reset function is
ATSC Digital Terrestrial TV
demodulator/decoder
2
C-bus bit SER (see Table 19).
2
C-bus bits SERTM
2
2
C-bus
C-bus
16
E
The TAP external interface has five pins whose functions
are described in Table 4.
Table 4 TAP external interface
I
The I
reads low-speed diagnostic information from the
TDA8961. The key features of the I
A typical system using the I
Fig.8. The TDA8961 is acting as a slave and is connected
to a master via the I
be noted that the SCL and SDA lines are connected to
separate pull-up resistors.
2
handbook, halfpage
TMS
TCK
TDI
TDO
TRST
XTERNAL INTERFACE
C-bus interface
I
Support for only 7-bit addressing and the ability to
externally modify the slave address.
2
C-bus data rate of up to 400 kbits/s
SIGNAL
SDA
2
SCL
C-bus interface writes control information to, and
Fig.8 Typical I
MASTER
I
2
C-BUS
Test mode select input
Test clock signal input
Test data input
Test data output
Test asynchronous reset input
2
C-bus lines SCL and SDA. It should
2
TDA8961
C system implementation.
2
C-bus interface is shown in
DESCRIPTION
Objective specification
2
C-bus interface are:
R pu
TDA8961
V DD
R pu
MGU089