NCP370 ON Semiconductor, NCP370 Datasheet
NCP370
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NCP370 Summary of contents
Page 1
... In this case overcurrent protection is activated to prevent accessory faults and battery discharge. Thanks to the NCP370 using an internal NMOS, the system cost and the PCB area of the application board are minimized. The NCP370 provides a negative going flag (FLAG) output which alerts the system that a fault has occurred. In addition, the device has ESD− ...
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... NCP370 Wall Adapter 1mF IN OUT 3 10 FLAG GND 4 9 RES DIR 8 5 RES REV 6 7 RES Ilim R limit INPUT DIR 10k Charger FLAG DIR REV 4.7mF GND Figure 1. Typical Application Circuit FUNCTIONAL BLOCK DIAGRAM Gate Driver and Reverse OCP ...
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... Reverse Charge Control Pin. In combination with DIR, the internal N−MOSFETs are turned on if Battery is applied on the OUT pin (See Tables 1 & 2). In reverse mode, the internal overcurrent protection is activated. When reverse mode is disabled, the NCP370 current consumption, into OUT pin, is drastically decreased to limit battery discharge. ...
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... Characteristics Symbols Input Voltage Range Input Voltage Vin Output Voltage Range Undervoltage Lockout Threshold UVLO Undervoltage Lockout Hysteresis UVLO Over voltage Lockout Threshold OVLO NCP370MUAITXG Overvoltage Lockout Hysteresis OVLO Over System Voltage Lockout OVLO Overvoltage Lockout Hysteresis OVLO Resistance R in ...
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... DIR = low and REV = low. The R higher during this mode allowing to handle few 10 mA This additional comparator allows to put higher input voltage (OVLO = 8.27 V typical) on the NCP370 during test production sequence (I.E: One Time Programming of the cell phone, PDA). This parameter is 25°C guaranteed only. ...
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The FLAG pin goes low as soon the input voltage exceeds the OVLO threshold or falls below the UVLO threshold. When the V level recovers normal condition, FLAG goes in high after a time delay, t (see Figure 3), following ...
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V in ton rev V out FLAG DIR REV micro−controller Table 1. FLAG TABLE DIR REV 1.5 < V < UVLO > OVLO UVLO < V < OVLO ...
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... To access to the reverse mode, DIR pin must be tied high (> 1.2) and REV must be tied high to low (< 0.55 V). In this case, the core of the NCP370 will be supplied by the battery, with a 2.5 V minimum voltage and 5.5 V maximum voltage. In this reverse state, both OCP and thermal modes are available ...
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... ESD Tests The NCP370 conforms to the IEC61000−4−2, level 4 on the Input pin (I.E Murata GRM188R61E105KA12D) must be placed close to the IN pins. If the IEC61000−4−2 is not a requirement, a 100 nF/25 V must be placed between IN and GND. The above configuration supports 15 kV (Air) and 8 kV (Contact) at the input per IEC61000− ...
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... R and Dropout DS(on) The NCP370 includes two internal low R N−MOSFETs to protect the system, connected on OUT pin, from overvoltage, negative voltage and reverse current protection. During normal operation, the R characteristics of the N−MOSFETs give rise to low losses on V pin. out ORDERING INFORMATION Device NCP370MUAITXG † ...
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... L 12X BOTTOM VIEW The products described herein (NCP370), may be covered by one or more U.S. patents. There may be other patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “ ...