NCP5314 ON Semiconductor, NCP5314 Datasheet
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NCP5314
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NCP5314 Summary of contents
Page 1
... NCP5314 Two/Three/Four−Phase Buck CPU Controller The NCP5314 provides full−featured and flexible control for the latest high−performance CPUs. The IC can be programmed as a two−, three− or four−phase buck controller, and the per−phase switching frequency can be as high as 1.2 MHz. Combined with external gate drivers and power components, the controller implements a compact, highly integrated multi− ...
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... ATX 3.3 V 1.5 k Typ ENABLE V ID5 V ID0 V ID1 ID2 ID2 ID3 ID3 ID4 ID4 4 PWRLS 3.3 V NCP5314 5 V FFB 1.5 k Typ PWRGD PWRGD 8 DRVON R1 R2 SGND Near Socket V FFB R fb Connection CS1 BST CS1 ...
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... CS3P 17 GND 18−21 GATE4−GATE1 OSC 24 I LIM 25 CS1P 26 CS1N 27 CS2P 28 CS2N 29 ENABLE NCP5314 Rating QFN LQFP QFN, Pad Soldered to PCB V V MAX MIN 18 V −0.3 V 7.0 V −0.3 V 7.0 V −0.3 V 7.0 V −0 −0.3 V 7.0 V −0.3 V 1.0 V −1.0 V 7.0 V −0.3 V 7.0 V − ...
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... Code is for reference only. †V No Load is the input to the error amplifier. OUT NCP5314 (0 C < T < 100 pF GATEx ) = 1.0 V, DAC Code 010100; unless otherwise noted) LIM V Code* ID (V) Connect V to COND, ...
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... Code is for reference only. †V No Load is the input to the error amplifier. OUT NCP5314 (0 C < T < 100 pF GATEx ) = 1.0 V, DAC Code 010100; unless otherwise noted) LIM V Code* ID (V) Connect V to COND, ...
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... Transient Response Time Channel Startup Offset Artificial Ramp Amplitude MOSFET Driver Enable (DRVON) Output High Output Low Pull−Down Resistance Source Current 2. Guaranteed by design, not tested in production. NCP5314 (0 C < T < 100 pF GATEx ) = 1.0 V, DAC Code 010100; unless otherwise noted) ...
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... Current Sense Common Mode Input Range General Electrical Specifications V Operating Current CC UVLO Start Threshold UVLO Stop Threshold UVLO Hysteresis 2. Guaranteed by design, not tested in production. NCP5314 (0 C < T < 1.0 V, DAC Code 010100; unless otherwise noted) LIM Test Conditions Measure GATEx ...
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... CS2P Current Sense Input 28 CS2N Current Sense Reference 29 ENABLE Enable NCP5314 Description VID−compatible logic input used to program the converter output voltage. All high on V −V generates fault. ID0 ID4 Voltage sensing pin for Power Good lower threshold. Input of PWM comparator for fast voltage feedback, and also the inputs of Power Good sense and overvoltage protection comparators A capacitor between this pin and ground programs the soft start time ...
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ENABLE UVLO Comparator − + − 0 − + 0.5 V 9.0 V 3.3 V 8.0 V Reference V ID5 V ID0 V VID = 11111x ID1 DAC V ID2 V DAC ...
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... Figure 5. OVP Threshold above VID versus Temperature 1000 3 Phase Mode 4 Phase Mode 100 10 k 100 k R (OHMS) OSC Figure 7. Oscillator Frequency versus Total R Value OSC NCP5314 235 230 VID = 111101 225 VID = 101101 220 80 100 120 0 700 650 600 550 500 ...
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... TEMPERATURE ( C) Figure 11. Soft−Start Charge Current versus Temperature 3.35 3.30 3.25 3.20 3.15 3.10 3.05 3. TEMPERATURE ( C) Figure 13. CS Amp to I LIM Temperature NCP5314 2.60 2.55 2.50 2.45 2.40 80 100 120 0 Figure 10. Current Sense to V 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 80 100 120 0 Figure 12. Current Sense Amplifier to PWM 110 105 100 ...
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... TYPICAL PERFORMANCE CHARACTERISTICS Enable V Fault REF UVLO Fault Fault Reset Fault Latch Fault DRVON SS COMP V OUT I OUT PWRGD NCP5314 100 TEMPERATURE ( C) Figure 15. V Operating Current versus CC Temperature Figure 16. Operating Waveforms http://onsemi.com 12 120 ...
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... PWM comparator. The purpose of the internal ramp is to compensate for propagation delays in the NCP5314. This provides greater design flexibility by allowing smaller external ramps, lower minimum pulse NCP5314 THEORY OF OPERATION Fixed Frequency Multi− ...
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... V, the duty cycle (D) will be 1.48/12.0 or 12.3%. Int_Ramp will be 100 mV/50% 12. mV. Realistic values for CSx CSx 0.015 F and 650 kHz. Using these and the previously mentioned formula, Ext_Ramp will be 15.0 mV. V COMP + 2.145 Vdc NCP5314 SWNODE by CORE OUT Internal Ramp CSA Out w/ ...
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... The worst case CSA input mismatch and will typically be within 4.0 mV. The difference in peak currents between NCP5314 To compensate the current sense signal, the values of R and C are chosen so that L/R ...
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... With fast (ideal) AVP, the peak−to−peak excursions are cut in half. In the slow AVP waveform, the NCP5314 output voltage is not repositioned quickly enough after current is stepped up and the upper limit is exceeded. ...
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... Accordingly, the gate outputs are capable of driving Ç Ç Ç a 100 pF load with typical rise and fall times of 5 ns. Ç Ç Ç Digital to Analog Converter (DAC) É É É The output voltage of the NCP5314 is set by means OUT −5.0% +5.0 % É É É ...
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... The microprocessor manufacturers usually specify a minimum number of ceramic capacitors. The designer must determine the number of bulk capacitors. NCP5314 4 as the gate drivers. The other gate drives may switch, so leave them unconnected. Single phase is best accomplished by using only Phase 2 as the switch controller ...
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... For increasing current: Dt INC + OUT ) NCP5314 For decreasing current: For typical processor applications with output voltages less than half the input voltage, the current will be increased much more quickly than it can be decreased. Thus, it may be ...
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... First, it will isolate the voltage source and the system from the noise generated in the switching supply. Second, it will limit the inrush current into the input capacitors at power up. Large NCP5314 − I inrush currents reduce the expected life of the input C,MIN capacitors. The inductor’ ...
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... Q GS1 GS2 GD Figure 26. MOSFET Switching Characteristics NCP5314 6. MOSFET and Heatsink Selection Power dissipation, package size and thermal requirements drive MOSFET selection. To adequately size the heat sink, the design must first predict the MOSFET power dissipation. Once the dissipation is known, the heat sink ...
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... All terms were defined in the previous discussion for the control MOSFET with the exception of: I RMS,SYNCH + [(I Lo,MAX Lo,MAX @ I Lo,MIN ) I Lo,MIN NCP5314 When the MOSFET power dissipations are known, the designer can calculate the required thermal impedance to maintain a specified junction temperature at the worst case (20) ambient operating temperature ...
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... C CSx CS1 MAX C CS1 R CSx MAX C CSx V CORE NCP5314 The output voltage droop will follow the equation: and R resistors FB where current sense amplifier ESR of Lo inductor ( load line resistance ( CS1P + COMP + − − G VDRP ...
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... Since the current information, sensed across the inductor part of the control loop, better stability is achieved if the current information is accurate and noise−free. The NCP5314 introduces a novel feature to achieve the best possible performance: differential current sense amplifiers. ...
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... Is Optimal. COMP Slews AMP Quickly Without Spiking or Ringing. V Overshoot and Monotonically Settles to Its Final Value. NCP5314 case, the output voltage will transition more slowly because COMP spikes upward as shown in Figure 34. Too much loop gain/bandwidth increases the risk of instability. In general, one should use the lowest loop gain/bandwidth possible to achieve acceptable transient response ...
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... Also, depending on the current sense points, the circuit board may add additional resistance. In general, the temperature coefficient of copper is +0.39% per _C. To set the level of the I pin: LIM V ILIM + (I OUT,LIM ) ILIM NCP5314 where the current limit threshold of the converter; OUT,LIM pin, the part half the inductor ripple current ...
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... 32X 32X NOTE 3 0. 0.05 C BOTTOM VIEW NCP5314 PACKAGE DIMENSIONS 32 PIN QFN SUFFIX CASE 485J−02 ISSUE NOTES: 1. DIMENSIONING AND TOLERANCING PER 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED 4. COPLANARITY APPLIES TO THE EXPOSED E (A3) A SEATING ...
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... REF 0.004 0.006 0.016 BSC 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. NCP5314/D ...