IR22141 International Rectifier, IR22141 Datasheet - Page 14

• Manufacturer Part Number: IR22141
• Description: HALF-BRIDGE GATE DRIVER IC
• Manufacturer: International Rectifier

IR2214/IR22141(SS)
FEATURES DESCRIPTION
1. Start-up sequence
At power supply start-up it is recommended to
keep FLT_CLR pin active until supply voltages
are properly established. This prevents spurious
diagnostic signals being generated. All protection
functions are operating independently from
FLT_CLR status and output driver status reflects
the input commands.
When bootstrap supply topology is used for
supplying the floating high side stage, the
following start-up sequence is recommended
(see also figure 12):
A minimum 15 s LIN and FLT-CLR pulse is
required.
14
1. Set Vcc
2. Set FLT_CLR pin to HIGH level
3. Set LIN pin to HIGH level and let the
4. Release LIN pin to LOW level
5. Release FLT_CLR pin to LOW level
bootstrap capacitor be charged
FLT_CLR
Figure 12 Start-up sequence
VCC
LIN
LO
ADVANCE DATA
2. Normal operation mode
After start-up sequence has been terminated, the
device becomes fully operative (see grey blocks
in the State Diagram).
HIN and LIN produce driver outputs to switch
accordingly, while the input logic checks the input
signals preventing shoot-through events and
including DeadTime (DT).
3. Shut down
The system controller can asynchronously
command the Hard ShutDown (HSD) through the
3.3 V compatible CMOS I/O FAULT/SD pin. This
event is not latched.
In a multi-phase system, FAULT/SD signals are
or-wired so the controller or one of the gate drivers
can force simultaneous shutdown to the other
gate drivers through the same pin.
4. Fault management
IR2214 is able to manage both the supply failure
(undervoltage lock out on both low and high side
circuits) and the desaturation of both power
transistors.
4.1 Undervoltage (UV)
The Undervoltage protection function disables the
driver’s output stage preventing the power device
being driven with too low voltages.
Both the low side (V
side (V
undervoltage function.
Undervoltage event on the V
V
forcing FAULT/SD pin low (see FAULT/SD section
and figure 14). This event disables both low side
and floating drivers and the diagnostic signal holds
until the under voltage condition is over. Fault
condition is not latched and the FAULT/SD pin is
released once V
CC
< UV
BS
supplied) are controlled by a dedicate
VCC-
) generates a diagnostic signal by
CC
becomes higher than UV
CC
supplied) and the floating
www.irf.com
CC
(when
VCC+
.