IR22141 International Rectifier, IR22141 Datasheet - Page 16

• Manufacturer Part Number: IR22141
• Description: HALF-BRIDGE GATE DRIVER IC
• Manufacturer: International Rectifier

IR2214/IR22141(SS)
16
The external sensing diode should have
BV>1200V and low stray capacitance (in order
to minimize noise coupling and switching de-
lays). The diode is biased by an internal pull-up
resistor R
IR2214) or by a dedicated circuit (see the active-
bias section for the IR22141). When V
creases, the voltage at DSH/L pin increases too.
Being internally biased to the local supply,
DSH/L voltage is automatically clamped. When
DSH/L exceeds the V
parator triggers (see figure 13). Comparator
output is filtered in order to avoid false
desaturation detection by externally induced
noise; pulses shorter than t
avoid detecting a false desaturation during IGBT
turn on, the desaturation circuit is disabled by a
Blanking signal (T
ure 13). This time is the estimated maximum
IGBT turn on time and must be not exceeded by
proper gate resistance sizing. When the IGBT is
DSH/L
(external hard
FAULT/SD
shutdown)
SY_FLT
(external
FLTCLR
(equal to V
hold)
BL
, see Blanking block in fig-
DESAT+
CC
DS
threshold the com-
/I
are filtered out. To
DS-
Figure 14: fault management diagram
internal
HOLD
or V
BS
/I
(hard shutdown)
internal FAULT
DS-
CE
for
in-
ADVANCE DATA
not completely saturated after T
is detected and the driver will turn off.
Eligible desaturation signals initiate the Soft
Shutdown sequence (SSD). While in SSD, the
output driver goes in high impedance and the
SSD pull-down is activated to turn off the IGBT
through SSDH/L pin. The SY_FLT output pin
(active low, see figure 14) reports the IR2214
status all the way long SSD sequence lasts (t
Once finished SSD, SYS_FLT releases, and
IR2214 generates a FAULT signal (see the
FAULT/SD section) by activating FAULT/SD pin.
This generates a hard shut down for both high
and low output stages (HO=LO=low). Each driver
is latched low until the fault is cleared (see
FLT_CLR).
Figure 14 shows the fault management circuit.
In this diagram DesatHS and DesatLS are two
internal signals that come from the output stages
(see figure 13).
Q
Q
SET
CLR
R
S
BL
, desaturation
www.irf.com
DesatHS
DesatLS
UVCC
SS
).