ADL5315 Analog Devices, ADL5315 Datasheet
ADL5315
Available stocks
Related parts for ADL5315
ADL5315 Summary of contents
Page 1
... Connecting RLIM directly to VPOS provides basic input short-circuit protection with the default current limit typical. The ADL5315 is available × 3 mm, 8-lead LFCSP and is specified for operation from −40°C to +85°C. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...
Page 2
... ADL5315 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 6 Theory of Operation ........................................................................ 9 Bias Control Interface .................................................................. 9 REVISION HISTORY 10/05—Revision 0: Initial Version Noise Performance ..................................................................... 10 Mirror Response Time............................................................... 10 Input Current Limiting ...
Page 3
... SET V = 4.0 V SET 2.7 V < V < POS V drops Ω INPT LIM V drops kΩ INPT LIM VPOS (Pin μA INPT INPT Rev Page ADL5315 Min Typ Max Unit 0.99 1.00 1.01 0.97 1.00 1.03 A/A 0.25 1. kHz 1 MHz 20 nA rms 0 V − ...
Page 4
... ADL5315 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Input Current at INPT Internal Power Dissipation θ (Soldered Exposed Paddle) JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 60 sec) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection ...
Page 5
... VPOS (Not to Scale) COMM 4 5 RLIM CONNECT Figure 2. 8-Lead LFCSP − 1.0 V for V < 6.5 V. For V POS POS − 1.0 V through 20 kΩ. Can be shorted to VSET for POS Rev Page ADL5315 ≥ 6.5 V range, V − 6 POS POS = 48 V/( kΩ). LIM LIM ...
Page 6
... ADL5315 TYPICAL PERFORMANCE CHARACTERISTICS 25°C, unless otherwise noted. POS SET SREF OUT A 2.0 +25°C, +70°C, +85°C, –40°C 0°C 0°C, –40°C 1.5 +25°C +70°C +85°C 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 1n 10n 100n 1μ 10μ I (A) INPT Figure 3. I Linearity vs ...
Page 7
... LIM V = 2.7V POS SET 5V POS SET SREF 2 0 – 8V, V POS –4 –6 –8 – (kΩ) LIM for Multiple Voltages LIM ADL5315 300 350 400 SREF = V SET SREF 80 90 100 ...
Page 8
... ADL5315 1.010 1.005 +85 +25 1.000 –40 0.995 0.990 (V) POS Figure 15. V − V vs. V for Multiple Temperatures POS INPT POS 0.99 0.993 0.996 0.999 1.002 I /I (A/A) OUT INPT Figure 16. Distribution for OUT INPT POS ...
Page 9
... CURRENT OUTPUT 390pF Figure 19. Basic Connections At the heart of the ADL5315 is a precision 1:1 current mirror with a voltage following characteristic that provides an adjustable bias voltage at the mirror input. This architecture uses a JFET input amplifier to drive the bipolar mirror and maintain stable V voltage, while offering very low leakage INPT current at the INPT pin ...
Page 10
... V fully settled. NOISE PERFORMANCE The noise performance for the ADL5315, defined as the rms noise current as a fraction of the output dc current, generally improves with increasing signal current. This partially results from the relationship between the quiescent collector current and the shot noise in the bipolar transistors ...
Page 11
... PIN photodiode or receiver module. Figure 22 shows a typical application where the ADL5315 is used to provide an accurate bias to a PIN diode while simultaneously mirroring the diode current to be measured by a translinear logarithmic amplifier. ...
Page 12
... PD PIN TIA DATA PATH Figure 24. Interfacing the ADL5315 to the AD8305 for High Accuracy PIN Power Monitoring Careful consideration should be made to the layout of the circuit board in this configuration. Leakage current paths in the board itself could lead to measurement errors at the output of the translinear log amp, particularly when measuring the low end of the ADL5315’ ...
Page 13
... EXTENDED OPERATING RANGE The ADL5315 is specified over an input current range mA, but the device remains fully functional over the full eight decade range specified for ADI’s flagship translinear logarithmic amplifier, the AD8304 (100 mA). Figure 25 and Figure 26 show the performance of the ADL5315 for this extended operating range vs ...
Page 14
... The setup in Figure 31 is used to measure the output current noise of the ADL5315. Batteries are used in numerous places to when INPT minimize introduced noise and remove the uncertainty resulting from the use of multiple dc supplies. In application, properly bypassed dc supplies provide similar results. The load ...
Page 15
... FET input op amp is used in a transimpedance amplifier configuration to allow for viewing on the TDS5104 oscilloscope. For signals greater than 30 μA, the ADA4899-1 replaced the AD8067 to avoid limiting the bandwidth of the ADL5315. The configuration in Figure 33 is used to measure pulsed. Q1 and R are used to generate the operating ...
Page 16
... IPD is desirable instead of a current. R2 Current Limiting. An external resistor to VPOS sets the current limit at INPT from mA V/(R LIM I = 3.7 mA. LIM C1, C2, R3 Supply Filtering/Decoupling. Figure 36. Component Side Layout ADL5315 1 INPT IOUT R4 4kΩ C3 VSET 2 SW1 SREF VPOS ...
Page 17
... Figure 38. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD × Body, Very Thin, Dual Lead (CP-8-1) Dimensions shown in millimeters Package Description 8-Lead LFCSP_VD 8-Lead LFCSP_VD Evaluation Board Rev Page 1.89 0.55 1.74 1.59 0.40 0. BOTTOM VIEW * EXPOSED PAD 0. 0.10 0.05 0.25 0.20 0.15 Package Option CP-8-1 CP-8-1 ADL5315 Branding Q0 Q0 ...
Page 18
... ADL5315 NOTES Rev Page ...
Page 19
... NOTES Rev Page ADL5315 ...
Page 20
... ADL5315 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05694–0–10/05(0) Rev Page ...