HT46C47 Holtek Semiconductor, HT46C47 Datasheet - Page 10

• Manufacturer Part Number: HT46C47
• Description: (HT46C46 / HT46C47) Cost-Effective A/D Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addi-
tion operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
time-out or executing the CLR WDT or HALT in-
struction. The PDF flag can be affected only by exe-
cuting the HALT or CLR WDT instruction or a
system power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or exe-
cuting the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can cor-
rupt the status register, precautions must be taken to
save it properly.
Interrupt
The device provides an external interrupt, internal
timer/event counter interrupt and A/D converter inter-
rupts. The Interrupt Control Register (INTC;0BH) con-
tains the interrupt control bits to set the enable or disable
and the interrupt request flags.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain in-
terrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of INTC may be set to
allow interrupt nesting. If the stack is full, the interrupt re-
quest will not be acknowledged, even if the related inter-
rupt is enabled, until the SP is decremented. If immediate
service is desired, the stack must be prevented from be-
coming full.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
Rev. 1.00
Bit No.
0
1
2
3
4
5
6
7
Label
EADI
ADF
EMI
EEI
ETI
EIF
TF
Controls the master (global) interrupt (1=enabled; 0=disabled)
Controls the external interrupt (1=enabled; 0=disabled)
Controls the Timer/Event Counter interrupt (1=enabled; 0=disabled)
Controls the A/D converter interrupt (1=enabled; 0=disabled)
External interrupt request flag (1=active; 0=inactive)
Internal Timer/Event Counter request flag (1=active; 0=inactive)
A/D converter request flag (1=active; 0=inactive)
Unused bit, read as 0
INTC (0BH) Register
HT46R46/HT46C46/HT46R47/HT46C47
10
a branch to a subroutine at specified location in the pro-
gram memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the con-
tents should be saved in advance.
External interrupts are triggered by a high to low transi-
tion of INT and the related interrupt request flag (EIF; bit
4 of INTC) will be set. When the interrupt is enabled, the
stack is not full and the external interrupt is active, a sub-
routine call to location 04H will occur. The interrupt re-
quest flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF;bit 5 of INTC), caused by a timer overflow. When the
interrupt is enabled, the stack is not full and the TF bit is
set, a subroutine call to location 08H will occur. The re-
lated interrupt request flag (TF) will be reset and the EMI
bit cleared to disable further interrupts.
The A/D converter interrupt is initialized by setting the
A/D converter request flag (ADF; bit 6 of INTC), caused
by an end of A/D conversion. When the interrupt is en-
abled, the stack is not full and the ADF is set, a subrou-
tine call to location 0CH will occur. The related interrupt
request flag (ADF) will be reset and the EMI bit cleared
to disable further interrupts.
During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, RET or
RETI may be invoked. RETI will set the EMI bit to enable
an interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Function
December 28, 2004