HT46R52 Holtek Semiconductor, HT46R52 Datasheet
HT46R52
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HT46R52 Summary of contents
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... Application Note HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM HA0004E HT48 & HT46 MCU UART Software Implementation Method HA0084E NiMH Battery Charger Demo Board - Using the HT46R52 Features Low-power fully static CMOS design Operating voltage: f =4MHz: 2 ...
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... Block Diagram Pin Assignment Rev. 1.40 HT46R51/HT46R52 2 July 12, 2005 ...
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... DD I Operating Current (Crystal OSC) DD1 I Operating Current (RC OSC) DD2 I Operating Current DD3 I Standby Current (WDT Enabled) STB1 Rev. 1.40 HT46R51/HT46R52 Description for the 18-pin DIP package DD +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... Test Conditions Min. Typ. V Conditions ...
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... External Reset Low Pulse Width RES t System Start-up Timer Period SST t Interrupt Pulse Width INT t A/D Clock Period AD t A/D Conversion Time ADC t A/D Sampling Time ADCS Note: t =1/f SYS SYS Rev. 1.40 HT46R51/HT46R52 Test Conditions Min. Typ. V Conditions load, system HALT 0.9V DD Configuration option =0.1V ...
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... PCL bits, PC10~PC8: Original PC counter, remain unchanged For the HT46R51, since the program counter is 10 bits wide (b0~b9), the b10 columns in the table are not ap- plicable. For the HT46R52, since the program counter is 11 bits wide (b0~b10) Rev. 1.40 HT46R51/HT46R52 For HT46R52, the program counter (PC bits wide and controls the sequence in which the instructions stored in the program ROM are executed ...
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... The program memory is used to store the program in- structions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 1024 14 (HT46R51) or 2048 14 (HT46R52) bits, ad- dressed by the Program Counter and table pointer. Certain locations in the ROM are reserved for special ...
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... For the Ht46R51, since the program counter is 10 bits wide (b0~b9), the b10 column in the table are not appli- cable For the HT46R52, since the program counter is 11 bits wide (b0~b10) Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter only ...
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... TO set by a WDT time-out Unused bit, read as 0 Rev. 1.40 HT46R51/HT46R52 Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, OR, XOR, CPL) Rotation (RL, RR, RLC, RRC) Increment and Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, SDZ ....) The ALU not only saves the results of a data operation but also changes the status register ...
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... For test mode used only. 7 Must be written otherwise may result in unpredictable operation. Rev. 1.40 HT46R51/HT46R52 routine call to location 0CH will occur. The related in- terrupt request flag (ADF) will be reset and the EMI bit cleared to disable further interrupts. During the execution of an interrupt subroutine, other in- ...
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... WDT oscillator still works with a period of approximately 5V. The WDT oscillator can be dis- abled by option to conserve power. Rev. 1.40 HT46R51/HT46R52 Watchdog Timer - WDT The clock source of the WDT is implemented by a dedi- cated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4) decided by options. This ...
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... However, if the Wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. Rev. 1.40 HT46R51/HT46R52 To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset may occur: ...
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... ADCR 0100 0000 0100 0000 ACSR ---- --00 ---- --00 Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 1.40 HT46R51/HT46R52 Reset Timing Chart Reset Configuration RES Reset RES Reset WDT Time-out (Normal Operation) (HALT) xxxx xxxx xxxx xxxx 00-0 1000 00-0 1000 ...
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... In the case of counter over- 8-Bit Timer/Event Counter Structure Rev. 1.40 HT46R51/HT46R52 flows, the counter is reloaded from the timer/event coun- ter register and issues an interrupt request the other two modes, i.e., event and timer modes. ...
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... T2 rising edge of instruction MOV A,[m] (m=12H, 14H or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Rev. 1.40 HT46R51/HT46R52 Function TMRC (0EH) Register Each I/O line has its own control register (PAC, PBC, PDC) to control the input/output configuration. With this ...
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... TMR timer/event counter Rev. 1.40 HT46R51/HT46R52 The PB can also be used as A/D converter inputs. The A/D function will be described later. There is a PWM function shared with PD0. If the PWM function is en- abled, the PWM signal will appear on PD0 (if PD0 is op- erating in output mode) ...
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... A/D conversion is completed. The START bit of the ADCR is used to begin the conver- sion of the A/D converter. Giving START bit a rising edge Rev. 1.40 HT46R51/HT46R52 (6+2) PWM Mode and falling edge means that the A/D conversion has started. In order to ensure that the A/D conversion is completed, the START should remain at 0 until the EOCB is cleared to 0 (end of A/D conversion) ...
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... ADCR (22H) Register PCR2 PCR1 PCR0 Rev. 1.40 HT46R51/HT46R52 ACS2 ACS1 ACS0 Analog Input Channel Selection Note: * undefined, cannot be used ...
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... ADRL register mov adrl_buffer,a ; save result to user defined register clr START set START ; reset A/D clr START ; start A Rev. 1.40 HT46R51/HT46R52 /8 as the A/D clock SYS /8 as the A/D clock SYS 18 July 12, 2005 ...
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... To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. Rev. 1.40 HT46R51/HT46R52 The relationship between V and V DD Note: V ...
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... This option is to decide whether a pull-high resistance is visible or not in the input mode of the I/O ports. PA, PB and PD are bit option. PFD selection. PA3: Level output or PFD output. PWM selection. PD0: level output or PWM output LVR selection. Enable or disable LVR function. Rev. 1.40 HT46R51/HT46R52 Options 20 July 12, 2005 ...
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... The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 1.40 HT46R51/HT46R52 C1 0pF 10k ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.40 HT46R51/HT46R52 Instruction Description 22 Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV ...
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... Otherwise the original instruction cycle is unchanged. (3) (1) (2) : and (4) : The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.40 HT46R51/HT46R52 Instruction Description 23 Flag Cycle Affected 2 None (2) 1 ...
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... Affected flag(s) TO PDF ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO PDF Rev. 1.40 HT46R51/HT46R52 ...
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... Operation Stack Program Counter+1 Program Counter Affected flag(s) TO PDF CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO PDF Rev. 1.40 HT46R51/HT46R52 addr ...
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... PDF 0* 0* CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO PDF Rev. 1.40 HT46R51/HT46R52 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO PDF Rev. 1.40 HT46R51/HT46R52 (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C ...
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... Operation Program Counter Affected flag(s) TO PDF MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO PDF Rev. 1.40 HT46R51/HT46R52 Program Counter addr OV Z ...
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... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO PDF Rev. 1.40 HT46R51/HT46R52 Program Counter+1 OV ...
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... Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 Affected flag(s) TO PDF Rev. 1.40 HT46R51/HT46R52 Stack Stack ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO PDF Rev. 1.40 HT46R51/HT46R52 ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO PDF Rev. 1.40 HT46R51/HT46R52 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO PDF Rev. 1.40 HT46R51/HT46R52 ([m]+1) ...
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... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO PDF Rev. 1.40 HT46R51/HT46R52 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO PDF Rev. 1.40 HT46R51/HT46R52 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO PDF Rev. 1.40 HT46R51/HT46R52 ...
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... Package Information 18-pin DIP (300mil) Outline Dimensions Symbol Min. A 895 B 240 C 125 D 125 295 I 335 0 Rev. 1.40 HT46R51/HT46R52 Dimensions in mil Nom. Max. 915 260 135 145 20 70 100 315 375 15 37 July 12, 2005 ...
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... SOP (300mil) Outline Dimensions Symbol Min. A 394 B 290 490 Rev. 1.40 HT46R51/HT46R52 Dimensions in mil Nom. Max. 419 300 20 510 104 July 12, 2005 ...
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... SSOP (150mil) Outline Dimensions Symbol Min. A 228 B 150 335 Rev. 1.40 HT46R51/HT46R52 Dimensions in mil Nom. Max. 244 158 12 347 July 12, 2005 ...
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... Key Slit Width T1 Space Between Flange T2 Reel Thickness SSOP 20S (150mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.40 HT46R51/HT46R52 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 16.8+0.3 0.2 22.2 0.2 40 July 12, 2005 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.40 HT46R51/HT46R52 Dimensions in mm 24+0.3 0.1 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.8 0.1 13.3 0.1 3.2 0.1 0.3 0.05 21.3 Dimensions in mm 16+0.3 0.1 8 0.1 1.75 0.1 7.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 6 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.40 HT46R51/HT46R52 42 July 12, 2005 ...