PDSP16116MC Zarlink Semiconductor, PDSP16116MC Datasheet
PDSP16116MC
Related parts for PDSP16116MC
PDSP16116MC Summary of contents
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The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional two's complement. The PDSP16116/A ...
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PDSP16116/A/MC The PDSP16116 has a number of features tailored for System applications Trap In multiply operations utilising Twos Complement Fractional notation, the - operation forms an invalid result not representable in the ...
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XR CEX REG C 16X16 O MULT M P '1' MUX REG ROUND ADD/SUB OVR CONX WTA AR15:13 WTB AI15:13 SOBFP EOPSS SFTR SFTA GWR4:0 WTOUT OER XI REG C C 16X16 O O MULT MUX ...
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PDSP16116/A/ Pin connections for 144 I/O power pin grid array package (bottom view Pin connections ...
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Signal PI14 PI15 WTOUT1 WTOUT0 SFTR0 SFTR1 SFTR2 OEI CONX ...
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PDSP16116/A/MC NORMAL MODE OPERATION When the MBFP mode select input is held low the ‘Normal’ mode of operation is selected. Complex Multiply operations that do not require Block Floating Point arithmetic. Multiplier Satge Complex two's complement fractional data is loaded ...
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Part No: PDSP11616/A/MC 16 By16 Bit Complex Multiplier Package Type: AC144 Pin No. Pin No. Con N/C ...
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PDSP16116/A/MC Part No: PDSP16116/A/ Bit Complex Multiplier Package Type: GC144 Pin No. Pin No. Con. 1 N/C 2 N/C 3 N/C 4 N/C 5 N/C 6 N ...
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WTB1 shift applied giving a shifter output format Bit Number – – – – – Weighting The ...
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PDSP16116/A/MC SOBFP (BFP MODE ONLY) Start of BFP: This input should be held low for the first cycle of the first pass of the BFP calculations (see Fig.7). It serves to reset the internal registers associated with BFP control. When ...
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In normal mode, these inputs perform a different function. They directly control the internal shifter at the output port as shown in Table 7. WTB1:0 FUNCTION 11 shift complex product one place to the left 00 no shift applied 01 ...
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PDSP16116/A/ SOBFP AR15:13 A PDSP1601/A SFTA PDSP16318 the end of each constituent pass of the FFT, the positions of the binary point supported may change to ...
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The butterfly operation The butterfly operation is the arithmetic operation which is repeated many times to produce an FFT. The PDSP16116A based butterfly processor performs this operation in a low power high accuracy chip set Figure 6 ...
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PDSP16116/A/MC Control of the FFT To enable the block floating point hardware to keep track of the data, the following signals are provided : - start of the FFT - end of current pass These inform the PDSP16116/A when an ...
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As FFT data consists of real and imaginary parts, either two PDSP1601As must be used (controlled by the same logic single PDSP1601/A could be used handling real and imaginary data on alternate cycles (using the same instructions for ...
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PDSP16116/A/MC ABSOLUTE MAXIMUM RATINGS Supply voltage V CC Input voltage V IN Output voltage V OUT Clamp diode current per I (see note 2) k Static discharge voltage (HBM) Storage temperature range T S Ambient temperature with power applied T ...
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Switching Characteristics Characteristic CLK rising edge to P-PORTS CLK rising edge to WTOUT1:0 CLK rising edge to GWR4:0 CLK rising edge to SFTA1:0 CLK rising edge to SFTR2:0 Setup port inputs to CLK rising edge Hold X ...
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