PDSP16116MC Zarlink Semiconductor, PDSP16116MC Datasheet - Page 11

• Manufacturer Part Number: PDSP16116MC
• Description: 16 by 16 Bit Complex Multiplier
• Manufacturer: Zarlink Semiconductor

In normal mode, these inputs perform a different function.
They directly control the internal shifter at the output port as
shown in Table 7.
SFTA1:0 (BFP & NORMAL MODES)
control. They allow shifting from one to four places to the right,
see Table 8. Depending on the relative weightings of the A-
words and the complex product, the A-word may have to be
shifted to the right to ensure compatible weightings at the
inputs to the PDSP16318 complex accumulator. (The two
words must have the same weighting if they are to be added).
function. If WTB1:0 is set to implement a left shift, then
overflow will occur if the data is fully 32 bits wide. This pin is
used to flag such an overflow. SFTA1 is not used in normal
mode.
OSEL1:0
OSEL1 instruction bits. These controls allow selection of the
output combination during the current cycle. (They are not
registered). These are four possible output configurations
that allow either complex outputs of the most or least
significant bytes, or real or imaginary outputs of the full 32 bit
word (see Table 4). OSEL0 and OSEL1 should both be tied
low when in BFP mode.
BFP MODE FFT APPLICATION
of the butterfly processor which will allow the following FFT
benchmarks:
within the PDSP16116 can be used to adaptively rescale data
throughout the course of the FFT so as to give high-resolution
results.
variation of the Radix-2 Decimation-In-Time FFT - e.g. the
WTB1:0
0 0
0 1
1 0
1 1
WTB1:0
11
00
01
10
In BFP mode, these signals act as as the A-word shift
In normal mode, SFTA0 performs a different a different
The outputs from the device are selected by the OSEL0 &
The PDSP16116 may be used as the main arithmetic unit
1024 point complex radix-2 transform in 517us
512 point complex radix-2 transform in 235us
256 point complex radix-2 transform in 106us
In addition, with pin MBFP tied high, the BFP circuitry
The BFP system on the PDSP16116 can be used with any
Table 8 - External A-word shift control
FUNCTION
Shift A-word 1 places to the right
Shift A-word 2 places to the right
Shift A-word 3 places to the right
Shift A-word 4 places to the right
FUNCTION
shift complex product one place to the left
no shift applied
shift complex product one place to the right
shift complex product two places to the right
Table 7 - Normal Mode Shift Control
Constant Geometry algorithm, the In-Place algorithm etc. An
N-point Radix-2 DIT FFT is split into log (N) passes. Each pass
consists of N/2 ‘butterflies’, each performing the operation:
Where W is the complex coefficient and A & B are the complex
data.
combined with two PDSP1601’s and two PDSP16318’s to
form a complete BFP butterfly processor. The PDSP16318’s
are used to perform the complex addition and subtraction of
the butterfly operation, while the PDSP1601’s are used to
match the data path of the A-word to the pipelining and shifting
operations within the PDSP16116.
butterfly processor, refer to application note AN59.
BFP MODE OPERATION
the FFT application described above. i.e. it is intended to
prevent data degredation during the course of an FFT
calculation. The operation of the PDSP16116 based BFP
butterfly processor (see Fig.4) is described below.
The Block Floating Point System
integer arithmetic system with some clever logic bolted on.
The object of the extra logic is to lend the system some of the
enormous dynamic range afforded by a true floating point
system without suffering the corresponding loss in
performance.
binary arithmetic weighting.
occupy the same position in every data word, as is normal in
integer arithmetic. However, during the course of the FFT, a
variety of weightings are used in the data words to increase the
dynamic range available. This situation is similar to that within
a true floating point system, though the range of numbers
representable is more limited. In the BFP system used in the
PDSP16116, there are, within any one pass of the FFT, four
possible positions of the binary point wihin the integer words.
To record the position of its binary point, each word has a 2-
bit word tag associated with it. By way of example, in a
particular pass we may have the following four positions of
binary point avaiable, each denoted by a certain value of word
tag:
A’ = A + B.W
B’ = A - B.W
Fig.4 illustrates how a single PDSP16116 may be
For more information on the theory and construction of this
The BFP mode on the PDSP16116 is intended for use in
A block floating point system is essentially an ordinary
The initial data used by the FFT should all have the same
XX.XXXXXXXXXXXX
XXX.XXXXXXXXXXX
XXXX.XXXXXXXXXX
XXXXX.XXXXXXXXX
i.e. the binary point should
word tag = 00
word tag = 01
word tag = 10
word tag = 11
PDSP16116/A/MC
11