DSP56F801 Motorola Inc, DSP56F801 Datasheet
DSP56F801
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DSP56F801 Summary of contents
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... Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F801 Rev. 16 01/2007 freescale.com ...
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General Description • MIPS operation at 60MHz core frequency • MIPS operation at 80MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • MCU-friendly instruction set supports both DSP ...
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Part 1 Overview 1.1 56F801 Features 1.1.1 Digital Signal Processing Core • Efficient 16-bit 56800 family controller engine with dual Harvard architecture • As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 × 16-bit ...
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Eleven multiplexed General Purpose I/O (GPIO) pins • Computer-Operating Properly (COP) watchdog timer • One dedicated external interrupt pin • External reset pin for hardware reset • JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging • Software-programmable, Phase Locked ...
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A key application-specific feature of the 56F801 is the inclusion of a Pulse Width Modulator (PWM) module. This modules incorporates six complementary, individually programmable PWM signal outputs to enhance motor control functionality. Complementary operation permits programmable dead-time insertion, and separate ...
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... Description Logic State True False True False are defined by individual product specifications. OH 56F801 Technical Data, Rev. 16 Product Documentation Order Number 56800EFM DSP56F801-7UM DSP56F801 56F801E Signal State 1 Voltage Asserted Deasserted ...
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Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F801 are organized into functional groups, as shown in and as illustrated in Figure 2-1. In signals present on a pin. Table 2-1 Functional Group Pin Allocations ...
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V DD Power Port V SS Ground Port V DDA Power Port V SSA Ground Port Other Supply Port EXTAL (GPIOB2) PLL and Clock or GPIO XTAL (GPIOB3) JTAG/OnCE™ Port * includes TCS pin which is reserved for factory use ...
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Power and Ground Signals No. of Pins Signal Name 4 V Power—These pins provide power to the internal structures of the chip, and should all be DD attached Analog Power—This pin is a dedicated power ...
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Table 2-5 PLL and Clock (Continued) No. of Signal Signal Pins Name Type During Reset 1 XTAL Output GPIOB3 Input/ Output 2.4 Interrupt and Program Control Signals Table 2-6 Interrupt and Program Control Signals No. of Signal Signal Pins Name ...
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Serial Peripheral Interface (SPI) Signals Table 2-8 Serial Peripheral Interface (SPI) Signals No. of Signal Signal Pins Name Type 1 MISO Input/Output Input/Output GPIOB6 1 MOSI Input/Output Input/Output GPIOB5 1 SCLK Input/Output Input/Output GPIOB4 1 SS Input GPIOB7 Input/Output ...
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Serial Communications Interface (SCI) Signals Table 2-9 Serial Communications Interface (SCI0) Signals No. of Signal Signal Pins Name Type 1 TXD0 Output GPIOB0 Input/Output 1 RXD0 Input GPIOB1 Input/Output 2.8 Analog-to-Digital Converter (ADC) Signals Table 2-10 Analog to Digital ...
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JTAG/OnCE Table 2-12 JTAG/On-Chip Emulation (OnCE) Signals No. of Signal Signal State During Pins Name Type 1 TCK Input Input, pulled (Schmitt) low internally 1 TMS Input Input, pulled (Schmitt) high internally 1 TDI Input Input, pulled (Schmitt) high ...
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The 56F801 DC and AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization ...
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Characteristic Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to case Junction to center of case I/O pin power dissipation Power dissipation Junction to center of case Notes: 1. ...
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DC Electrical Characteristics Table 3-4 DC Electrical Characteristics Operating Conditions: Characteristic Input high voltage (XTAL/EXTAL) Input low voltage (XTAL/EXTAL) 1 Input high voltage [GPIOB(2:3)] 1 Input low voltage [GPIOB(2:3)] Input high voltage (Schmitt trigger inputs) Input low voltage (Schmitt ...
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Table 3-4 DC Electrical Characteristics (Continued) Operating Conditions: Characteristic V supply current DD 7 Run (80MHz operation) 7 Run (60MHz operation) 8 Wait Stop Low Voltage Interrupt, external power supply Low Voltage Interrupt, internal power supply 11 Power on Reset ...
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IDD Digital 120 Figure 3-1 Maximum Run IDD vs. Frequency (see Note 7. in 3.3 AC Electrical Characteristics Timing waveforms in Section 3.3 table. In Figure 3-2 the levels of V Input Signal Midpoint1 Fall ...
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Data1 Valid Data1 Data Invalid State Data Active 3.4 Flash Memory Characteristics 1 Mode XE Standby L Read H Word Program H Page Erase H Mass Erase address enable, all rows are disabled when ...
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Operating Conditions: Characteristic Program time Erase time Mass erase time 1 Endurance 1 Data Retention The following parameters should only be used in the Manual Word Programming Mode PROG/ERASE to NVSTR set up time NVSTR hold time NVSTR hold time ...
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IFREN XADR XE YADR YE DIN PROG Tnvs NVSTR IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR 22 Tadh Tads Tprog Tpgs Thv Figure 3-4 Flash Program Cycle Terase Figure 3-5 Flash Erase Cycle 56F801 Technical Data, Rev. 16 Tpgh Tnvh ...
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IFREN XADR XE MAS1 YE=SE=OE=0 ERASE Tnvs NVSTR 3.5 External Clock Operation The 56F801 device clock is derived from either 1) an internal crystal oscillator circuit working in conjunction with an external crystal external frequency source ...
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As shown in should be used. The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a capacitive load on each of the oscillator pins (XTAL and ...
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... See Figure 3-9 for details on using the recommended connection of an external clock driver. 2. May not exceed 60MHz for the DSP56F801FA60 device. 3. The high or low pulse width must be no smaller than 6.25ns or the chip will not function. 4. Parameters listed are guaranteed by design. External ...
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When changing clocks, the user must ensure that the clock source is not switched until the desired ...
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Figure 3-11 Typical Relaxation Oscillator Frequency vs. Temperature Figure ...
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... The PLL is optimized for 8MHz input crystal. 2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f User Manual. ZCLK = Will not exceed 60MHz for the DSP56F801FA60 device. 4. This is the minimum time required after the PLL setup is changed to ensure reliable operation. 28 Table 3-10 PLL Timing ...
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Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing Operating Conditions: Characteristic RESET Assertion to Address, Data and Control Signals High Impedance Minimum RESET Assertion Duration OMR Bit 6 = ...
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RESET t RAZ A0–A15, D0–D15 PS, DS, RD, WR Figure 3-13 Asynchronous Reset Timing IRQA, IRQB Figure 3-14 External Interrupt Timing (Negative-Edge-Sensitive) A0–A15 IDM , IRQA IRQB General Purpose I/O Pin t ...
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IRQA, IRQB A0–A15, PS, DS, RD, WR Figure 3-16 Interrupt from Wait State Timing t IW IRQA A0–A15, PS, DS, RD, WR Figure 3-17 Recovery from Stop State Using Asynchronous Interrupt Timing IRQA A0–A15 PS, DS, RD, WR Figure 3-18 ...
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Serial Peripheral Interface (SPI) Timing Operating Conditions: Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data setup time required for ...
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SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) Figure 3-19 SPI Master Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref) t ...
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SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 3-21 SPI Slave Timing (CPHA = 0) SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input ...
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Quad Timer Timing Operating Conditions: Characteristic Timer input period Timer input high/low period Timer output period Timer output high/low period 1. In the formulas listed clock cycle. For 80MHz operation 12.5ns. 2. Parameters listed are ...
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RXD SCI receive data pin (Input) TXD SCI receive data pin (Input) 3.10 Analog-to-Digital Converter (ADC) Characteristics Characteristic ADC input voltages Resolution 3 Integral Non-Linearity Differential Non-Linearity Monotonicity 5 ADC internal clock Conversion range Conversion time Sample time Input capacitance ...
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Table 3-15 ADC Characteristics (Continued) Characteristic 5 Total Harmonic Distortion 5 Signal-to-Noise plus Distortion 5 Effective Number of Bits 5 Spurious Free Dynamic Range Bandwidth ADC Quiescent Current (both ADCs) V Quiescent Current (both ADCs) REF 1. For optimum ADC ...
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JTAG Timing Operating Conditions: Characteristic 2 TCK frequency of operation TCK cycle time TCK clock pulse width TMS, TDI data setup time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state TRST ...
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TCK (Input) TDI TMS (Input) TDO (Output) TDO (Output ) TDO (Output) Figure 3-28 Test Access Port Timing Diagram TRST (Input) t TRST Freescale Semiconductor t DS Input Data Valid Figure ...
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Part 4 Packaging 4.1 Package and Pin-Out Information 56F801 This section contains package and pin-out information for the 48-pin LQFP configuration of the 56F801. TDO TD1 TD2 PIN 1 /SS MISO MOSI SCLK TXDO RXD0 DE ...
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Table 4-1 56F801 Pin Identification by Pin Number Pin No. Signal Name Pin No. 1 TD0 2 TD1 3 TD2 MISO 6 MOSI 7 SCLK 8 TXD0 RXD0 12 DE ...
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AB T 0.200 AC T BASE METAL 0.080 AC T ...
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Part 5 Design Considerations 5.1 Thermal Design Considerations An estimation of the chip junction temperature Equation Where ambient temperature ° package junction-to-ambient thermal resistance °C/W θJA ...
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Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. • Use the value obtained by the equation (T determined by ...
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Bypass the V and capacitor such as a tantalum capacitor. • Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal. • Consider all device loads as well as ...
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... Low Profile Plastic Quad Flat Pack (LQFP) 56F801 3.0–3.6 V Low Profile Plastic Quad Flat Pack (LQFP) *This package is RoHS compliant. 46 Pin Package Type Count 56F801 Technical Data, Rev. 16 Ambient Frequency Order Number (MHz) 80 DSP56F801FA80 60 DSP56F801FA60 80 DSP56F801FA80E* 60 DSP56F801FA60E* Freescale Semiconductor ...
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Freescale Semiconductor 56F801 Technical Data, Rev. 16 Electrical Design Considerations 47 ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2005. All rights reserved. DSP56F801 Rev. 16 01/2007 ...