DSP56002RC40 Motorola Inc, DSP56002RC40 Datasheet

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SEMICONDUCTOR TECHNICAL DATA 24-BIT DIGITAL SIGNAL PROCESSOR The DSP56002 is a MPU-style general purpose Digital Signal Processor (DSP) composed of an efficient 24-bit DSP core, program and data memories, various peripherals, and support circuitry. The DSP56000 core is fed by ...

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SECTION 1 PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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FEATURES Digital Signal Processing Core • Efficient 24-bit DSP56000 core • Million Instructions Per Second (MIPS instruction cycle at 80 MHz MIPS, 30.3 ns instruction cycle at 66 MHz • ...

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Features Peripheral and Support Circuits • Byte-wide host interface (HI) with Direct Memory Access (DMA) support (or fifteen Port B GPIO lines) • SSI support: – Supports serial devices with one or more industry-standard codecs, other DSPs, microprocessors, and Motorola-SPI-compliant ...

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PRODUCT DOCUMENTATION The three documents listed in the following table are required for a complete description of the DSP56002 and are necessary to design properly with the part. Documentation is available from one of the following locations (see back cover ...

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Product Documentation vi DSP56002/D, Rev. 3 MOTOROLA ...

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SIGNAL/PIN DESCRIPTIONS INTRODUCTION DSP56002 signals are organized into twelve functional groups, as summarized in Table 1-1 . Table 1-1 Signal Functional Group Allocations Functional Group Power (V ) CCX Ground (GND ) X PLL and Clock Address Bus Data Bus ...

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Signal/Pin Descriptions Introduction Power Inputs: V PLL CCP V Clock Output CCCK 4 V Internal Logic CCQ 3 V Address Bus CCA 3 V Data Bus CCD V Bus Control CCC CCH V SSI/SCI CCS Grounds: GND ...

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POWER Power Names V Analog PLL Circuit Power —This line is dedicated to the analog PLL circuits CCP and must remain noise-free to ensure stable PLL frequency and performance. Ensure that the input voltage to this line is well-regulated and ...

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Signal/Pin Descriptions Ground GROUND Ground Names GND Analog PLL Circuit Ground —This line supplies a dedicated quiet ground P connection for the analog PLL circuits and must remain relatively noise-free to ensure stable PLL frequency and performance. Ensure that this ...

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PLL AND CLOCK State Signal Signal during Name Type Reset EXTAL Input Input XTAL Output Chip- driven CKOUT Output Chip- driven CKP Input Input PCAP Input/ Indeter- Output minate MOTOROLA Table 1-4 PLL and Clock Signals Signal Description External Clock/Crystal ...

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Signal/Pin Descriptions PLL and Clock Table 1-4 PLL and Clock Signals (Continued) State Signal Signal during Name Type Reset PINIT Input Input PLOCK Output Indeter- minate 1-6 Signal Description PLL Initialization Source—The value of this signal at reset defines the ...

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ADDRESS BUS State Signal Signal during Names Type Reset A0–A15 Output Tri-stated Address Bus—These signals specify the address for external DATA BUS State Signal Signal during Names Type Reset D0–D23 Input/ Tri-stated Data Bus—These signals provide the bidirectional data bus ...

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Signal/Pin Descriptions Bus Control BUS CONTROL State Signal Signal during Name Type Reset PS Output Tri-stated Program Memory Select—PS is asserted low for external program DS Output Tri-stated Data Memory Select—DS is asserted low for external data memory X/Y Output ...

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Table 1-7 Bus Control Signals (Continued) State Signal Signal during Name Type Reset BN Output Pulled low WT Input Input WR Output Tri-stated Write Enable—WR is asserted low during external memory write RD Output Tri-stated Read Enable—RD is asserted low ...

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Signal/Pin Descriptions Interrupt and Mode Control INTERRUPT AND MODE CONTROL Table 1-8 Interrupt and Mode Control Signals State Signal Signal Name during Type Reset MODA/IRQA Input Input MODB/IRQB Input Input 1-10 Signal Description Mode Select A/External Interrupt Request A—This input ...

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Table 1-8 Interrupt and Mode Control Signals (Continued) State Signal Signal Name during Type Reset MODC/NMI Input Input RESET Input Input MOTOROLA Signal Description Mode Select C/Non-maskable Interrupt Request—This input has two functions select the initial chip operating ...

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Signal/Pin Descriptions Host Interface (HI) Port HOST INTERFACE (HI) PORT State Signal Signal during Name Type Reset H0–H7 Input Tri-stated Host Data Bus (H0–H7)—This data bus transfers data between or Output PB0–PB7 HA0–HA2 Input Tri-stated Host Address 0—Host Address 2 ...

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State Signal Signal during Name Type Reset HEN Input Tri-stated Host Enable—This input enables a data transfer on the host data PB12 Input or Output HREQ Open Tri-stated Host Request—This signal is used by the Host Interface to drain Output ...

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Signal/Pin Descriptions Serial Communications Interface Port SERIAL COMMUNICATIONS INTERFACE PORT Table 1-10 Serial Communications Interface (SCI+) Signals State Signal Signal Name during Type Reset RXD Input Tri-stated Receive Data (RXD)—This input receives byte-oriented data and PC0 Input or Output TXD ...

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SYNCHRONOUS SERIAL INTERFACE PORT Table 1-11 Synchronous Serial Interface (SSI) Signals State Signal Signal Name during Type Reset SC0 Input Tri- or stated Output PC3 SC1 Input Tri- or stated Output PC4 SC2 Input Tri- or stated Output PC5 MOTOROLA ...

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Signal/Pin Descriptions Synchronous Serial Interface Port Table 1-11 Synchronous Serial Interface (SSI) Signals (Continued) State Signal Signal Name during Type Reset SCK Input Tri- or stated Output PC6 SRD Input Tri- stated PC7 Input or Output STD Output Tri- stated ...

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TIMERS State Signal Signal Name during Type Reset TIO Input Tri- or stated Output MOTOROLA Table 1-12 Timer Signals Signal Description Timer Input/Output—The TIO signal provides an interface to the timer/event counter module. When the module functions as an external ...

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Signal/Pin Descriptions On-Chip Emulation Port On-CHIP EMULATION PORT Table 1-13 On-Chip Emulation (OnCE) Signals State Signal Signal Name during Type Reset DSI/OS0 Input Low or Output Output DSCK/OS1 Input Low or Output Output 1-18 Signal Description Debug Serial Input/Chip Status ...

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Table 1-13 On-Chip Emulation (OnCE) Signals (Continued) State Signal Signal Name during Type Reset DSO Output Pulled high DR Input Input MOTOROLA Signal Description Debug Serial Output—Data contained in one of the OnCE controller registers is provided through the DSO ...

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Signal/Pin Descriptions On-Chip Emulation Port 1-20 DSP56002/D, Rev. 3 MOTOROLA ...

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GENERAL CHARACTERISTICS The DSP56002 is fabricated in high-density HCMOS with TTL compatible inputs and outputs. MAXIMUM RATINGS This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid ...

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Specifications Thermal characteristics Table 2-1 Absolute Maximum Ratings (GND = 0 V) Rating Supply Voltage All Input Voltages Current Drain per Pin excluding V Operating Temperature Range Storage Temperature THERMAL CHARACTERISTICS Characteristic Symbol Junction-to-ambient R 1 thermal resistance Junction-to-case R ...

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DC ELECTRICAL CHARACTERISTICS Table 2-3 DC Electrical Characteristics Characteristics Supply Voltage Input High Voltage • EXTAL • RESET • MODA, MODB, MODC • All other inputs Input Low Voltage • EXTAL • MODA, MODB, MODC • All other inputs Input ...

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Specifications AC Electrical Characteristics AC ELECTRICAL CHARACTERISTICS The timing waveforms in the AC Electrical Characteristics are tested with a V maximum of 0.5 V and a V MODA, MODB, and MODC. These pins are tested using the input levels set ...

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INTERNAL CLOCKS For each occurrence and MF are PLL division and multiplication factors set in registers. Characteristics Internal Operation Frequency Internal Clock High Period • With PLL disabled • With PLL enabled and MF 4 • With ...

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Specifications External Clock (EXTAL Pin) EXTERNAL CLOCK (EXTAL PIN) The DSP56002 system clock may be derived from the on-chip crystal oscillator as shown in Figure 2- may be externally supplied. An externally supplied square wave voltage source should ...

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EXTAL ET 1 NOTE: The midpoint is V Num Characteristics Frequency of Operation (EXTAL Pin) 1 Clock Input High • With PLL disabled (46.7% – 53.3% duty cycle) • With PLL enabled (42.5% – 57.5% duty cycle) 2 Clock Input ...

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Specifications Phase Lock Loop (PLL) Characteristics PHASE LOCK LOOP (PLL) CHARACTERISTICS Table 2-6 Phase Lock Loop (PLL) Characteristics Characteristics VCO frequency when PLL enabled 4 PLL external capacitor (PCAP pin CCP Notes: 1. The ...

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Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies) (Continued) Num Characteristics 16a Minimum Edge-Triggered Interrupt Request Deassertion Width 17 Delay from IRQA, IRQB, NMI Assertion to External Memory Access Address Out Valid • Caused by First Interrupt ...

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Specifications RESET, Stop, Mode Select, and Interrupt Timing Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies) (Continued) Num Characteristics 28 Delay from Level Sensitive IRQA Assertion to Fetch of First Interrupt Instruction (when exiting ‘Stop’) • Internal ...

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RESET MODA, MODB MODC Figure 2-6 Operating Mode Select Timing A0–A15 IRQA IRQB NMI General Purpose I/O 18 IRQA IRQB NMI Figure 2-7 External Level-Sensitive Fast Interrupt Timing MOTOROLA RESET, Stop, Mode Select, and Interrupt Timing 14 ...

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Specifications RESET, Stop, Mode Select, and Interrupt Timing IRQA, IRQB NMI IRQA, IRQB NMI Figure 2-8 External Interrupt Timing (Negative Edge-Triggered) CKOUT IRQA, IRQB NMI A0–A15, DS, PS X/Y Figure 2-9 Synchronous Interrupt from Wait State Timing 25 IRQA A0–A15, ...

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HOST I/O (HI) TIMING TTL loads L Note: Active low lines should be “pulled up” manner consistent with the ac and dc specifications. Table 2-8 Host I/O Timing (All Frequencies) Num Characteristics ...

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Specifications Host I/O (HI) Timing Table 2-8 Host I/O Timing (Continued)(All Frequencies) (Continued) Num Characteristics 47 Delay from HEN Deassertion to HREQ Assertion for RXL Read 48 Delay from HEN Deassertion to HREQ Assertion for TXL Write 49 Delay from ...

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HREQ (Output) RXH HEN Read (Input HA2–HA0 Address Valid (Input) 41 HR/W (Input H0–H7 Data (Output) Valid Figure 2-13 Host Read Cycle (Non-DMA Mode) HREQ (Output) TXH HEN Write (Input HA2–HA0 Address Valid (Input) ...

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Specifications Host I/O (HI) Timing HREQ (Output RXH HACK Read (Input Data H0–H7 Valid (Output) HREQ (Output TXH HACK Write (Input) 33 H0–H7 Data (Output) Valid 2- RXM Read 37 38 Data ...

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SERIAL COMMUNICATION INTERFACE (SCI) TIMING TTL loads Synchronous Clock Cycle Time (For internal clock, t SCC Control Register and T ) The minimum t C. Table 2-9 SCI Synchronous Mode Timing ...

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Specifications Serial Communication Interface (SCI) Timing RCLK TCLK (Output) 59 TXD RXD RCLK TCLK (Input) TXD RXD Figure 2-17 SCI Synchronous Mode Timing 1X TCLK (Output) TXD Note: In the wire-OR mode, TXD can be pulled ...

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SYNCHRONOUS SERIAL INTERFACE (SSI) TIMING TTL loads SSI clock cycle time SSICC TXC (SCK Pin) = Transmit Clock RXC (SC0 or SCK Pin) = Receive Clock FST (SC2 Pin) = Transmit ...

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Specifications Synchronous Serial Interface (SSI) Timing Num Characteristics 89 Data In Hold Time After RXC Falling Edge 90 FSR Input (bl) High Before RXC Falling Edge 91 FSR Input (wl) High Before RXC Falling Edge 92 FSR Input Hold Time ...

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Num Characteristics 101A TXC Falling Edge to Data Out High 2 Impedance 102 FST Input (bl) Setup Time Before TXC Falling Edge 103 FST Input (wl) to Data Out Enable from High Impedance 104 FST Input (wl) Setup Time Before ...

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Specifications Synchronous Serial Interface (SSI) Timing 81 TXC (Input/ Output) FST (Bit) Out FST (Word) Out Data Out 102 FST (Bit) In FST (Word) In Flags Out Note: In the Network mode, output flag transitions can occur at the start ...

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RXC (Input/Output) FSR (Bit) Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In Flags In MOTOROLA Synchronous Serial Interface (SSI) Timing First Bit Figure 2-20 SSI ...

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Specifications External Bus Asynchronous Timing EXTERNAL BUS ASYNCHRONOUS TIMING TTL loads Number of Wait States (0 to 15), as determined by BCR register Capacitance Derating: The DSP56002 External Bus Timing Specifications ...

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Table 2-12 External Bus Asynchronous Timing (Continued) No. Characteristics Min 117 BG Deassertion Duration • During Wait T C – mode • All other cases – 5.5 H 118 Delay from Address, 0 Data, and Control Bus ...

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Specifications External Bus Asynchronous Timing Table 2-12 External Bus Asynchronous Timing (Continued) No. Characteristics Min 126 RD Deassertion Address Not Valid 127 Address Valid to RD Deassertion • • WS ...

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Table 2-12 External Bus Asynchronous Timing (Continued) No. Characteristics Min 136 RD Deassertion to WR Assertion • • WS > A0–A15, PS DS, X/Y, RD, WR D0–D23 Figure ...

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Specifications External Bus Asynchronous Timing A0–A15, DS, PS, X/Y (See Note) RD 120 135 WR 123 D0–D23 Note: During Read-Modify-Write instructions, the address lines do not change state. Figure 2-22 External Bus Asynchronous Timing 2-28 127 131 129 122 121 ...

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EXTERNAL BUS SYNCHRONOUS TIMING TTL loads L Capacitance Derating: The DSP56002 external bus timing specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability ...

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Specifications External Bus Synchronous Timing T0 CKOUT A0–A15 DS, PS X/Y 140 RD 141 WR D0–D23 BN 171 EXTAL 170 Note: During Read-Modify-Write Instructions, the address lines do not change states. Figure 2-23 Synchronous Bus Timing 2- ...

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Table 2-14 Bus Strobe/Wait Timing No. Characteristics 150 First CKOUT transition to BS Assertion 151 WT Assertion to first CKOUT transition (setup time) 152 First CKOUT transition to WT Deassertion for Minimum Timing 153 WT Deassertion to first CKOUT transition ...

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Specifications External Bus Synchronous Timing Table 2-14 Bus Strobe/Wait Timing (Continued) No. Characteristics 163 BR Deassertion to second CKOUT transition for Minimum Timing 164 First CKOUT transition to BG Assertion 165 First CKOUT transition to BG Deassertion 170 EXTAL to ...

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CKOUT 162 BR BG Figure 2-24 Synchronous Bus Request / Bus Grant Timing MOTOROLA External Bus Synchronous Timing 164 163 DSP56002/D, Rev. 3 Specifications 165 AA0396 2-33 ...

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Specifications External Bus Synchronous Timing T0 CKOUT 140 A0–A15, PS, DS, X/Y 150 BS 151 WT 143 RD D0–D23 141 WR D0–D23 Note: During Read-Modify-Write instructions, the address lines do not change state. However, BS will deassert before asserting again ...

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A0–A15, PS, DS, X/Y 155 BS 157 156 WT 131 RD D0–D23 120 WR D0–D23 Note: During Read-Modify-Write instructions, the address lines do not change state. However, BS will deassert before asserting again for the write cycle. Figure 2-26 Asynchronous ...

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Specifications OnCE Port Timing OnCE PORT TIMING TTL loads L Num Characteristics 230 DSCK Low 231 DSCK High 232 DSCK Cycle Time 233 DR Asserted to DSO (ACK) Asserted 234 DSCK High to DSO ...

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Num Characteristics 250B DR Assertion Width to Recover from Stop state and 1 enter Debug mode • Stable External Clock,OMR Bit • Stable External Clock,OMR Bit • Stable External Clock,PCTL Bit 17= 1 251 ...

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Specifications OnCE Port Timing DSCK (Input) DSO (Output) 236 DSI (Input) Note: High Impedance, external pull-down resistor Figure 2-29 OnCE Data I/O To Status Timing DSCK (Input) 234 DSO (Output) Note: High Impedance, external pull-down resistor OS1 (Output) 241 DSO ...

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CKOUT OS0–OS1 (Output) (See Note) Note: High Impedance, external pull-down resistor Figure 2-32 OnCE CKOUT To Status Timing DSCK (Input) Figure 2-33 OnCE Read Register to Next Command Timing CKOUT DR (Input) DSO (Output) Figure 2-34 Synchronous Recovery from Wait ...

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Specifications OnCE Port Timing DR (Input) DSO (Output) Figure 2-36 Asynchronous Recovery from Stop State 2-40 250 251 DSP56002/D, Rev. 3 AA0508 MOTOROLA ...

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TIMER TIMING TTL loads L Num Characteristics 260 TIO Low 261 TIO High 262 Synchronous Timer Setup Time from TIO (input) Assertion to CKOUT Rising Edge 263 Synchronous Timer Delay Time from CKOUT Rising ...

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Specifications Timer Timing CKOUT TIO (Output) Figure 2-39 External Pulse Generation fetch the instruction MOVE X0,X:(R0); X0 contains the new value of TIO CKOUT A0–A15 PS, DS EXTP, X/Y TIO (Output) 2-42 264 ; and R0 contains the address of ...

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PIN-OUT AND PACKAGE INFORMATION This sections provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated for each package. The DSP56002 is available ...

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Packaging Pin-out and Package Information PQFP Package Description Top and bottom views of the PQFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs. H4/PB4 18 H3/PB3 V CCH H2/PB2 GND H H1/PB1 H0/PB0 RXD/PC0 TXD/PC1 GND ...

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GND D D21 D20 V CCD Orientation Mark D19 (Chamfered Edge D18 on Top Side) GND D D17 D16 D15 D14 GND D D13 D12 V CCD D11 D10 GND D GND Q V CCQ GND ...

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Packaging Pin-out and Package Information The DSP56002 signals that may be programmed as General Purpose I/O are listed with their primary function in Table 3-9 . Table 3-1 DSP56002 General Purpose I/O Pin Identification in PQFP Package Pin Number 24 ...

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Table 3-2 DSP56002 Signal Identification by PQFP Pin Number Pin No. Signal Name 1 EXTAL 2 V CCQ 3 GND Q 4 HA2/PB10 5 GND H 6 HA1/PB9 7 HA0/PB8 8 HACK/PB14 9 V CCH 10 HEN/PB12 11 GND H ...

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Packaging Pin-out and Package Information Table 3-2 DSP56002 Signal Identification by PQFP Pin Number (Continued) Pin No. Signal Name 76 A10 77 A11 78 A12 79 V CCA 80 A13 81 GND A 82 A14 83 A15 ...

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Table 3-3 DSP56002 PQFP Pin Identification by Signal Name Signal Name Pin No A10 76 A11 77 A12 78 A13 ...

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Packaging Pin-out and Package Information Table 3-3 DSP56002 PQFP Pin Identification by Signal Name (Continued) Signal Name Pin No. GND HA0 7 ...

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Power and ground pins have special considerations for noise immunity. See Section 4 Design Considerations. Table 3-4 DSP56002 Power Supply Pins in PQFP Package Pin Number 124 122 89 102 ...

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Packaging Pin-out and Package Information Table 3-4 DSP56002 Power Supply Pins in PQFP Package (Continued) Pin Number 127 129 3-10 Power Supply V CCQ GND Q V CCP GND ...

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VIEW 0.016 H L-M N 0.010 T L TIPS 0.012 H L 0.002 132X 0.008 U D ...

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Packaging Pin-out and Package Information TQFP Package Description Top and bottom views of the TQFP package are shown in Figure 3-4 and Figure 3-5 with their pin-outs. NC 109 D0 D1 GND CCD D4 D5 GND ...

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NC DSCK/OS1 NC GNDC CCC TIO SRD/PC7 V CCQ GND Q SC1/PC4 NC GNDS STD/PC8 SC2/PC5 SCK/PC6 V CCS SC0/PC3 SCLK/PC2 GNDS TXD/PC1 RXD/PC0 H0/PB0 H1/PB1 GND H H2/PB2 V CCH H3/PB3 ...

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Packaging Pin-out and Package Information The DSP56002 signals that may be programmed as General Purpose I/O are listed with their primary function in Table 3-9. Table 3-5 DSP56002 General Purpose I/O Pin Identification in TQFP Package Pin Number 44 43 ...

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Table 3-6 DSP56002 Signal Identification by TQFP Pin Number Pin No. Signal Name D22 3 D23 4 MODC/NMI 5 MODB/IRQB 6 MODA/IRQA 7 GND CK 8 CKOUT 9 V CCCK 10 RESET 11 CKP 12 V CCP ...

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Packaging Pin-out and Package Information Table 3-6 DSP56002 Signal Identification by TQFP Pin Number (Continued) Pin No. Signal Name 76 DSI/OS0 X/Y 79 GND CCA ...

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Table 3-7 DSP56002 TQFP Pin Identification by Signal Name Signal Name Pin No A10 100 A11 101 A12 102 A13 ...

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Packaging Pin-out and Package Information Table 3-7 DSP56002 TQFP Pin Identification by Signal Name (Continued) Signal Name Pin No. GND HA0 25 ...

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Table 3-7 DSP56002 TQFP Pin Identification by Signal Name (Continued) Signal Name Pin No CCQ V 58 CCQ V 89 CCQ V 123 CCQ V 50 CCS X/Y 78 MOTOROLA Pin-out and Package Information ...

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Packaging Pin-out and Package Information Power and ground pins have special considerations for noise immunity. See the section Design Considerations. Table 3-8 DSP56002 Power Supply Pins in TQFP Package Pin Number 81 93 103 105 66 ...

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Table 3-8 DSP56002 Power Supply Pins in TQFP Package (Continued) Pin Number 123 124 MOTOROLA Pin-out and Package Information Power Supply V CCQ GND Q V CCP GND P ...

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Packaging Pin-out and Package Information 0. PIN 1 144 IDENT PLATING BASE D METAL 0. SECTION J1-J1 (ROTATED 90) ...

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PGA Package Description Top and bottom views of the PGA package are shown in Figure 3-7 and Figure 3-8 with their pin-outs. Orientation Mark GND V GND V Q CCQ Q CCQ B GND V ...

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Packaging Pin-out and Package Information GND GND H6 HACK HEN CCH C GND RXD H2 HREQ H D TXD CCH E GND SCLK ...

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The DSP56008 signals that may be programmed as General Purpose I/O are listed with their primary function in Table 3-9. Table 3-9 DSP56002 General Purpose I/O Pin Identification in PGA Package Pin Number E11 D11 C11 E10 D10 B12 A11 ...

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Packaging Pin-out and Package Information Table 3-10 DSP56002 Signal Identification by PGA Pin Number Pin No. Signal Name A1 GND CCQ A3 GND CCQ A5 GND CCQ A7 GND Q A8 ...

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Table 3-10 DSP56002 Signal Identification by PGA Pin Number (Continued) Pin No. Signal Name J1 V CCD A15 J10 RD J11 WR J12 WT J13 GND S K1 GND ...

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Packaging Pin-out and Package Information Table 3-11 DSP56002 PGA Pin Identification by Signal Name Signal Name Pin No A10 L5 ...

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Table 3-11 DSP56002 PGA Pin Identification by Signal Name (Continued) Signal Name Pin No. GND L13 S H0 E11 H1 D11 H2 C11 H3 E10 H4 D10 H5 B12 H6 A11 H7 B11 HA0 C9 HA1 B9 HA2 A9 HACK ...

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Packaging Pin-out and Package Information Power and ground pins have special considerations for noise immunity. See the section Design Considerations. Table 3-12 DSP56002 Power Supply Pins in PGA Package Pin Number N10 M13 ...

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Table 3-12 DSP56002 Power Supply Pins in PGA Package (Continued) Pin Number K13 J13 L13 -T- -A- -B- C Figure 3-9 132-pin Ceramic Pin Grid Array (PGA) Package Mechanical Information ...

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Packaging Ordering Drawings ORDERING DRAWINGS Complete mechanical information regarding DSP56002 packaging is available by facsimile through Motorola's Mfax™ system. Call the following number to obtain information by facsimile: The Mfax automated system requests the following information: • The receiving facsimile ...

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DESIGN CONSIDERATIONS HEAT DISSIPATION An estimation of the chip junction temperature, T equation: Equation Where ambient temperature ˚ package junction-to-ambient thermal resistance ˚C power dissipation in ...

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Design Considerations Heat Dissipation estimations obtained from R performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: • To minimize ...

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ELECTRICAL DESIGN CONSIDERATIONS This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. ...

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Design Considerations Power Consumption POWER CONSUMPTION Power dissipation is a key issue in portable DSP applications. The following describes some factors which affect current consumption. Current consumption is described by the formula: Equation where: ...

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Current consumption test code: org jmp org movep move move move move nop rep move rep mov clr move rep mac move jmp TP1 nop jmp MOTOROLA p:RESET MAIN p:MAIN #$180000,x:$FFFD #0,r0 #0,r4 #$00FF, m0 #$00FF, m4 #256 r0,x:(r0)+ #256 ...

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Design Considerations Host Port Considerations HOST PORT CONSIDERATIONS Careful synchronization is required when reading multibit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected. The situation exists in the host ...

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CANCELLING A PENDING HOST COMMAND EXCEPTION The host processor may elect to clear the HC bit to cancel the Host Command Exception request at any time before it is recognized by the DSP. Because the host does not know exactly ...

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Design Considerations Package Compatibility PACKAGE COMPATIBILITY The PQFP and TQFP packages are designed so that a single Printed Circuit Board (PCB) can accommodate either package. The two package pinouts are similarly sequenced. Proper orientation of each package with the smaller ...

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... Voltage Plastic Quad Flat Pack DSP56002 5 V Plastic Thin Quad Flat Ceramic Pin Grid Array MOTOROLA SECTION Package Type Pin Count 132 (PQFP) 144 Pack (TQFP) 132 DSP56002/D, Rev Frequency Order Number (MHz) 40 DSP56002FC40 66 DSP56002FC66 80 DSP56002FC80 40 DSP56002PV40 66 DSP56002PV66 80 DSP56002PV80 40 DSP56002RC40 5-1 ...

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OnCE and Mfax are trademarks of Motorola, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor ...