DSP56002RC40 Motorola Inc, DSP56002RC40 Datasheet - Page 39
DSP56002RC40
Manufacturer Part Number
DSP56002RC40
Description
24-BIT DIGITAL SIGNAL PROCESSOR
Manufacturer
Motorola Inc
Datasheet
1.DSP56002RC40.pdf
(110 pages)
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HOST I/O (HI) TIMING
C
MOTOROLA
L
Num
= 50 pF + 2 TTL loads
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
HEN/HACK Assertion Width
HEN/HACK Deassertion Width
Host Data Input Setup Time Before HEN/HACK
Deassertion
Host Data Input Hold Time After HEN/HACK
Deassertion
HEN/HACK Assertion to Output Data
HEN/HACK Assertion to Output Data Valid
HEN/HACK Deassertion to Output Data High
Impedance
Output Data Hold Time After HEN/HACK
Deassertion
HR/W Low Setup Time Before HEN Assertion
HR/W Low Hold Time After HEN Deassertion
HR/W High Setup Time to HEN Assertion
HR/W High Hold Time After HEN/HACK
Deassertion
HA0–HA2 Setup Time Before HEN Assertion
HA0–HA2 Hold Time After HEN Deassertion
DMA HACK Assertion to HREQ Deassertion
DMA HACK Deassertion to HREQ Assertion
Active from High Impedance
Note: Active low lines should be “pulled up” in a manner consistent with the ac and
•
•
•
•
•
•
•
•
CVR, ICR, ISR, RXL Read
IVR, RXH/M Read
Write
Between Two TXL Writes
Between Two CVR, ICR, ISR, RXL Reads
For DMA RXL Read
For DMA TXL Write
All other cases
dc specifications.
5
6
Table 2-8 Host I/O Timing (All Frequencies)
Characteristics
DSP56002/D, Rev. 3
1
1
2
4
4,5
3
T
L
2T
2T
T
T
+ T
L
C
Min
C
C
2.5
26
13
13
—
—
+ T
+ 31
4
3
0
0
3
0
3
0
3
3
0
C
+ 31
+ 31
+ T
C
H
Host I/O (HI) Timing
Max
—
—
—
26
18
—
—
—
—
—
—
—
45
—
—
—
—
—
—
—
—
—
Specifications
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-13
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