DSP56F826 Motorola, DSP56F826 Datasheet - Page 8

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DSP56F826

Manufacturer Part Number
DSP56F826
Description
16-bit Digital Signal Processor
Manufacturer
Motorola
Datasheet

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All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always enabled.
Exceptions:
8
1.
2.
CLKO
Signal
Name
Table 3. DSP56F826 Signal and Package Information for the 100 Pin LQFP
D10
D11
D12
D13
D14
D15
DE
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DS
When a pn is owned by GPIO, then the pull-up may be disabled under software control.
TCK has a weak pull-down circuit always active.
Pin No.
65
34
35
36
37
38
39
40
41
42
43
44
46
47
48
49
50
98
28
Output
Input/Output
Output
Output
Type
DSP56F826 Preliminary Technical Data
Clock Output—This pin outputs a buffered clock signal. By programming
the CLKO Select Register (SLKOSR), the user can select between
outputting a version of the signal applied to XTAL and a version of the DSP
master clock at the output of the PLL. The clock frequency on this pin can be
disabled by programming the CLKO Select Register (CLKOSR).
Data Bus— D0–D15 specify the data for external program or data memory
accesses. D0–D15 are tri-stated when the external bus is inactive.
Debug Event—DE provides a low pulse on recognized debug events.
Data Memory Select—DS is asserted low for external data memory access.
Description

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