LM3S316-IQN25 Luminary Micro, Inc., LM3S316-IQN25 Datasheet - Page 109
LM3S316-IQN25
Manufacturer Part Number
LM3S316-IQN25
Description
Microcontroller
Manufacturer
Luminary Micro, Inc.
Datasheet
1.LM3S316-IQN25.pdf
(409 pages)
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8.1
Figure 8-1. GPIO Module Block Diagram
8.2
October 8, 2006
PA0
PA1
PA2
PA3
PA4
PA5
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Block Diagram
Functional Description
Important:
I2CSCL
I2CSDA
U0Rx
U0Tx
SSIClk
SSIFss
PWM2
PWM3
C0-
C0+
SSIRx
SSITx
All GPIO pins are inputs by default (GPIODIR=0 and GPIOAFSEL=0), with the
exception of the five JTAG pins (PB7 and PC[3:0]. The JTAG pins default to their
JTAG functionality (GPIOAFSEL=1). Asserting a Power-On-Reset (POR) or an
external reset (RST) puts both groups of pins back to their default state.
Comparator
Analog
UART0
PWM1
SSI
JTAG
I
2
C
GPIO Port C
C0o
Preliminary
CCP1
CCP3
Fault
UART1
Timer0
Timer1
PWM0
PWM0
PWM1
CCP2
U1Rx
CCP0
U1Tx
LM3S316 Data Sheet
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PE0
PE1
109
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