LM3S600 Bookham Technology, Inc., LM3S600 Datasheet - Page 134
LM3S600
Manufacturer Part Number
LM3S600
Description
Microcontroller
Manufacturer
Bookham Technology, Inc.
Datasheet
1.LM3S600.pdf
(378 pages)
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General-Purpose Input/Outputs (GPIOs)
GPIO Interrupt Clear (GPIOICR)
GPIO Port A base: 0x4000.4000
GPIO Port B base: 0x4000.5000
GPIO Port C base: 0x4000.6000
GPIO Port D base: 0x4000.7000
GPIO Port E base: 0x4002.4000
Offset 0x41C
Type W1C, reset 0x0000.0000
134
Reset
Reset
Type
Type
Bit/Field
31:8
7:0
RO
RO
31
15
0
0
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C
The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the
corresponding interrupt edge detection logic register. Writing a 0 has no effect.
RO
RO
30
14
0
0
reserved
Name
IC
RO
RO
29
13
0
0
RO
RO
28
12
0
0
reserved
RO
RO
W1C
Type
27
11
0
0
RO
RO
RO
26
10
0
0
Reset
0x00
0x00
RO
RO
25
0
9
0
Preliminary
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPIO Interrupt Clear
The IC values are defined as follows:
RO
RO
Value
24
0
8
0
reserved
0
1
Description
Corresponding interrupt is unaffected.
Corresponding interrupt is cleared.
W1C
RO
23
0
7
0
W1C
RO
22
0
6
0
W1C
RO
21
0
5
0
W1C
RO
20
0
4
0
IC
W1C
RO
19
0
3
0
W1C
RO
18
0
2
0
October 01, 2007
W1C
RO
17
0
1
0
W1C
RO
16
0
0
0
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