DS2704 Maxim Integrated Products, DS2704 Datasheet - Page 13

• Manufacturer Part Number: DS2704
• Description: 1280-Bit EEPROM
• Manufacturer: Maxim Integrated Products

I/O SIGNALING
The 1-Wire bus requires strict signaling protocols to ensure data integrity. The four protocols used by the DS2704
are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write 1, and read data.
The bus master initiates all these types of signaling except the presence pulse.
The initialization sequence required to begin any communication with the DS2704 is shown in Figure 5. A presence
pulse following a reset pulse indicates that the DS2704 is ready to accept a net address command. The bus master
transmits (Tx) a reset pulse for t
1-Wire bus line is then pulled high by the pullup resistor. After detecting the rising edge on the DQ pin, the DS2704
waits for t
Figure 5. 1-Wire Initialization Sequence
WRITE-TIME SLOTS
A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level to a logic-low
level. There are two types of write-time slots: write 1 and write 0. All write-time slots must be t
a 1ms minimum recovery time, t
and t
write 0 occurs. The sample window is illustrated in Figure 6. 1-Wire Write and Read Time Slots. For the bus master
to generate a write 1 time slot, the bus line must be pulled low and then released, allowing the line to be pulled high
less than t
pulled low and held low for the duration of the write-time slot.
READ-TIME SLOTS
A read-time slot is initiated when the bus master pulls the 1-Wire bus line from a logic-high level to a logic-low level.
The bus master must keep the bus line low for at least 1ms and then release it to allow the DS2704 to present valid
data. The bus master can then sample the data t
time slot, the DS2704 releases the bus line and allows it to be pulled high by the external pullup resistor. All read-
time slots must be t
timing specifications in the Electrical Characteristics table for more information.
LOW0_MIN
DQ
PDH
RDV
and then transmits the presence pulse for t
after the line falls. If the line is high when sampled, a write 1 occurs. If the line is low when sampled, a
after the start of the write time slot. For the host to generate a write 0 time slot, the bus line must be
SLOT
LINE TYPE LEGEND:
in duration with a 1ms minimum recovery time, t
t
RSTL
BUS MASTER ACTIVE LOW
BOTH BUS MASTER AND
DS2704 ACTIVE LOW
REC
RSTL
, between cycles. The DS2704 samples the 1-Wire bus line between t
. The bus master then releases the line and goes into receive mode (Rx). The
t
PDH
RDV
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from the start of the read-time slot. By the end of the read-
PDL
.
t
PDL
DS2704 ACTIVE LOW
RESISTOR PULLUP
t
RSTH
REC
, between cycles. See Figure 6 and the
SLOT
in duration with
PACK+
PACK-
LOW1_MAX