AN2008 Motorola / Freescale Semiconductor, AN2008 Datasheet - Page 6

• Manufacturer Part Number: AN2008
• Description: Evaluating ColdFire in a 68K Target System: MCF5307 to MC68EC020 Gateway Reference Design
• Manufacturer: Motorola / Freescale Semiconductor

MC68EC020 PGA—MCF5307FT, Gateway Reference Design
The test mode signals on the MCF5307 microprocessor determine whether the device operates in BDM or
JTAG test mode. The MTMOD0 is the key signal that determines this selection so the MTMOD[3:1] signals
should be tied low to ground. To ensure that the MCF5307 microprocessor assumes control of the bus, the
bus grant (/BG) signal must be tied to ground through a 4.7K resistor. Similarly, the test clock signal must
be tied to ground (again through a 4.7K resistor) when it is not being used.
The MCF5307 microprocessor should be powered via 3.3V supply and connected to appropriate ground
connections as indicated on the circuit diagram.
1.2.2 RS232 Communications Port
The schematic in shows how a standard 5V tolerant RS232 communications port can be created using a
Motorola MC145407DW 5V driver / receiver. The MC145407DW combines three drivers and receivers to
meet electrical standards EIA-232-E and CCITT V28. The six drivers on the MC145407 are designed to
guarantee a charge pump output of ± 5 V while operating from a single 5V power supply. RS232 logic levels
are obtained by an internal voltage doubler and inverter arrangement that converts +5V to ± 10 V.
The RS232 control signals are fed into the Gateway board through connector CON8 that is powered via a
5V DC supply. Capacitors C20-23 provide high /low frequency bypass to minimize noise in the system.
Capacitors C18 and C19 are the charge pump capacitors that determine the slew rate of the charge pump
therefore governing the overall operation of the MC145407DW chip. Setting the value of C18 and C19 to
10uF, gives the same slew rate output characteristics of the MC145407DW chip as that given in the electrical
specification section of the data sheet. Note, the correct polarity of the electrolytic capacitors must be
observed when constructing the gateway board!
(Consult http://www.mot-sps.com/books/dl136/pdf/mc145407rev1.pdf for more information on this
device.)
1.2.3 MC5307FT Microprocessor Connection
The diagram in Appendix E shows the jumper connections to the MC5307 Microprocessor. Four 50-way
connectors are used to breakout the signals from the chip into the dual in line connectors (DIL). Connectors
J3-2, J4-2, J5-2 and J6-2 allow the MC68EC020 target hardware control signals to connect directly to the
control signals on the MCF5307 via the Gateway Reference board. This diagram also shows jumper JP16
which is used to connect the reset on the target device to the ColdFire reset.
1.2.4 FSRAM and Flash Memory Connections
The schematic shown in Appendix F illustrates the connections of the on-board FLASH ROM
(MBM29F800A3BT80) and the 128Kx8 Asynchronous Fast SRAM (MCM6926AWJ8). This configuration
provides 1 Mbyte of Flash ROM and 4 MBytes of FSRAM memory.
The MCM6926A is a 1,048,576 bit static random access memory organized as 131,072 words of 8 bits. The
static design of this part eliminates the need for external clocks or timing strobes and only requires three
control signals for operation – output enable (/G), chip enable (/E) and write enable (/W).
Chip select 5 (/CS5) controls the chip selects for all the FSRAM chips and the output enable signal (/OE)
on the MCF5307 microprocessor controls the output enable of all memory chips – both the FLASH ROM
and FSRAM. Write enable of the FSRAM chips is independently controlled through the (Byte) Write
Enable signals (/WE[0:3]) directly from the MCF5307 microprocessor. Chip select 5 was chosen for the
FSRAM to allow lower order chip selects to be used for interfacing to devices on the target hardware.
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MCF5307 to MC68EC020 Gateway Reference Design