CY22050 Cypress Semiconductor, CY22050 Datasheet - Page 5

• Manufacturer Part Number: CY22050
• Description: One-PLL General Purpose Flash Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07006 Rev. *D
DC Electrical Characteristics
AC Electrical Characteristics
I
I
I
I
V
V
I
I
I
I
I
I
Notes:
OH3.3
OL3.3
OH2.5
OL2.5
VDD
VDDL3.3
VDDL2.5
DDS
OHZ
OLZ
Parameter
4. Not 100% tested, guaranteed by design.
5. I
6. Use CyClocksRT to calculate actual I
7. Skew value guaranteed when outputs are generated from the same divider bank. See Logic Block Diagram for more information.
8. Jitter measurement will vary. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, V
Parameter
IH
IL
and output load. For more information, refer to the application note, “Jitter in PLL-based Systems: Causes, Effects, and Solutions,” available at http://www.cy-
press.com, or contact your local Cypress Field Applications Engineer.
VDD
[5,6]
t3
t4
t5
t6
t3
t4
t10
t1
t2
LO
LO
currents specified for two CLK outputs running at 125 MHz, two LCLK outputs running at 80 MHz, and two LCLK outputs running at 66.6 MHz.
[7]
[8]
HI
HI
[5,6]
[5,6]
[4]
[4]
PLL lock time
Output frequency,
commercial temp
Output frequency,
industrial temp
Output duty cycle
Rising edge slew
rate (V
Falling edge slew
rate (V
Rising edge slew
rate (V
Falling edge slew
rate (V
Skew
Clock jitter
Output High Current
Output Low Current
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Supply Current
Supply Current
Supply Current
Power-Down Current
Output Leakage
DDL
DDL
DDL
DDL
Name
Name
= 2.5V)
= 2.5V)
= 3.3V)
= 3.3V)
VDD
and I
Clock output limit, 3.3V
Clock output limit, 2.5V
Clock output limit, 3.3V
Clock output limit, 2.5V
Duty cycle is defined in Figure 2; t1/t2
f
Duty cycle is defined in Figure 2; t1/t2
f
Output clock rise time, 20% – 80% of V
Defined in Figure 3
Output clock fall time, 80% – 20% of V
Defined in Figure 3
Output clock rise time, 20% – 80% of
V
Output clock fall time, 80% – 20% of
V
Output-output skew between related outputs
Peak-to-peak period jitter (see Figure 4)
OUT
OUT
DD
DD
VDDL
/V
/V
> 166 MHz, 50% of V
< 166 MHz, 50% of V
V
V
V
V
CMOS levels, 70% of V
CMOS levels, 30% of V
AV
V
V
V
V
DDL
DDL
OH
OL
OH
OL
DDL
DDL
DD
DD
for specific output frequency configurations.
DD
= 0.5V, V
= 0.5V, V
= V
= V
. Defined in Figure 3
. Defined in Figure 3
= V
= V
/V
Current (V
Current (V
DD
DDL
DDL
DD
DDL
Current
Description
– 0.5V, V
= AV
= AV
– 0.5V, V
DD
DDL
DDL
DDL
/V
DD
DD
Description
= 2.5V
DDL
= 3.465V
= 3.465V
= 3.465V)
= 2.625V)
DD
DD
DD
DDL
= 3.3V
/V
DD
DD
DDL
= 2.5V
= 3.3V
DDL
DDL
.
.
0.08 (80 kHz)
0.08 (80 kHz)
0.08 (80 kHz)
0.08 (80 kHz)
Min.
0.6
0.6
0.8
0.8
40
45
Min.
0.7
12
12
8
8
0
Typ.
0.30
Typ.
250
DDL
1.2
1.2
1.4
1.4
50
50
24
24
16
16
45
25
17
(2.5V or 3.3V), temperature,
166.6
166.6
Max.
200
150
250
Max.
CY22050
60
55
1.0
0.3
3
50
10
Page 5 of 9
MHz
MHz
MHz
MHz
V/ns
V/ns
V/ns
V/ns
Unit
Unit
ms
V
V
mA
mA
mA
mA
mA
mA
mA
ps
ps
%
%
µA
µA
DD
DD