CY22801 Cypress Semiconductor, CY22801 Datasheet - Page 5

• Manufacturer Part Number: CY22801
• Description: Universal Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 001-15571 Rev. **
AC Electrical Characteristics
Test Circuit
Notes
f
f
f
DC
t
t
t
t
t
5. Skew value guaranteed when outputs are generated from the same divider bank.
6. Jitter measurement may vary. Actual jitter is dependent on input jitter and edge rate, number of active outputs, input and output frequencies, supply voltage,
REFC
REFD
OUT
3
4
5
6
10
[5]
[6]
Parameter
V
temperature, and output load. For more information, refer to the application note, Jitter in PLL-based Systems: Causes, Effects, and Solutions.
DD
0.1μF
Figure 2. Test Circuit Diagram
Reference Frequency - crystal
Reference Frequency - driven
Output Frequency
Output Duty Cycle
Rising Edge Slew Rate
Falling Edge Slew Rate
Skew
Clock Jitter
PLL Lock Time
OUTPUTS
GND
Name
[2]
C
Duty Cycle is defined in
Output Clock Fall Time, 80% - 20% of V
Output-output skew between related outputs
Peak-to-peak period jitter
Output Clock Rise Time, 20% - 80% of V
LOAD
CLKout
Timing Definitions
Description
CLK
CLK
Figure 3. Duty Cycle Definition; DC = t2/t1
Figure
Figure 4. Rise and Fall Time Definitions
3, 50% of V
50%
t1
t2
t3
DD
20%
DD
80%
DD
Min
0.8
0.8
45
8
1
1
–
–
–
50%
t4
Typ
250
1.4
1.4
50
–
–
–
–
–
CY22801
Max
133
200
250
Page 5 of 7
30
55
–
–
–
3
MHz
MHz
MHz
V/ns
V/ns
Unit
ms
ps
ps
%
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