CY2305 Cypress Semiconductor, CY2305 Datasheet - Page 3

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CY2305

Manufacturer Part Number
CY2305
Description
CY2305 and CY2309 as PCI and SDRAM Buffers
Manufacturer
Cypress Semiconductor
Datasheet

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ALTERA
0
Output To Output Skew
The skew between CLKOUT and the other outputs is not dy-
namically adjusted by the loop. All MUST have the same load
on them to achieve zero output to output skew. If the other
outputs are less loaded than CLKOUT, they will lead it; and if
the other outputs are more loaded, they will lag the CLKOUT.
The relationship that exists between the CLKOUT and the rest
REF
CLKOUT
CLKA1
CLKA4
CLKB1
CLKB4
REF input and CLKA1-CLKB4 loaded
equally, with CLKOUT loaded more
Zero Delay Buffer Timing diagrams with different loading configurations.
Advanced
REF input and all
outputs loaded equally
REF
CLKOUT
CLKA1
CLKA4
CLKB1
CLKB4
Zero Delay
REF input and CLKA1-CLKB4 loaded
equally, with CLKOUT loaded less
3
CY2305 and CY2309 as PCI and SDRAM Buffers
REF
CLKOUT
CLKA1
CLKA4
CLKB1
CLKB4
of the outputs is that they all start the rising edge at the same
time, but different loads will cause them to have different rise
times and different times crossing the measurement thresh-
olds. Since CLKOUT is the only output that is monitored, it will
be the output that has the zero delay from the reference and
the other clocks will be relative to CLKOUT and their loading
differences.
Delayed

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